Patents by Inventor Hyun-Chul Shon

Hyun-Chul Shon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7112486
    Abstract: The present invention provides a method for fabricating a semiconductor device having a dual gate dielectric structure capable of obtaining a simplified process and improving device reliability. The method includes the steps of: forming an insulation layer on a substrate; forming a nitride layer on the insulation layer; selectively etching the nitride layer in a predetermined region of the substrate; performing a radical oxidation process to form an oxide layer on the insulation layer and the etched nitride layer; forming a gate conductive layer on the oxide layer; and performing a selective etching process to the gate conductive layer, the oxide layer, the nitride layer and the insulation layer, so that the first dielectric structure formed in the predetermined region includes the insulation layer and the oxide layer and the second gate dielectric structure formed in regions other than the predetermined region includes the insulation layer, the nitride layer and the oxide layer.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: September 26, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Heung-Jae Cho, Se-Aug Jang, Kwan-Yong Lim, Jae-Geun Oh, Hong-Seon Yang, Hyun-Chul Shon
  • Publication number: 20060008996
    Abstract: The present invention provides a method for fabricating a semiconductor device having a dual gate dielectric structure capable of obtaining a simplified process and improving device reliability. The method includes the steps of: forming an insulation layer on a substrate; forming a nitride layer on the insulation layer; selectively etching the nitride layer in a predetermined region of the substrate; performing a radical oxidation process to form an oxide layer on the insulation layer and the etched nitride layer; forming a gate conductive layer on the oxide layer; and performing a selective etching process to the gate conductive layer, the oxide layer, the nitride layer and the insulation layer, so that the first dielectric structure formed in the predetermined region includes the insulation layer and the oxide layer and the second gate dielectric structure formed in regions other than the predetermined region includes the insulation layer, the nitride layer and the oxide layer.
    Type: Application
    Filed: December 20, 2004
    Publication date: January 12, 2006
    Inventors: Heung-Jae Cho, Se-Aug Jang, Kwan-Yong Lim, Jae-Geun Oh, Hong-Seon Yang, Hyun-Chul Shon