Abstract: The present invention relates to an additive composition including a counteragent, and more particularly, to an additive composition for preparation of polyolefins, which improve flowability of a nucleating agent and exhibits excellent transparency, by applying a counteragent of a specific structure to a sorbitol nucleating agent which is an additive used in preparation of polyolefins.

Abstract: A memory controller and method of operating same are described. The memory controller includes a central processing unit providing re-transmission control signal, an error check block determining whether an error exists in data received from a host and generating a corresponding error check signal, and a re-transmission request unit receiving the control signal and the error check signal, communicating a request to the host for an error-correcting re-transmission operation when an error exists in the received data, and communicating a request for an extending re-transmission operation when error does not exist in the received data.

Abstract: A method of communicating data between an external storage device and a USB host via a USB device is disclosed. The method includes receiving data from the USB host; and either (1) directly communicating the received data to the external storage device via an exclusive bus, or (2) indirectly communicating the received data to the external storage device via a USB bus, separate from the exclusive bus.

Abstract: A memory controller and method of operating same are described. The memory controller includes a central processing unit providing re-transmission control signal, an error check block determining whether an error exists in data received from a host and generating a corresponding error check signal, and a re-transmission request unit receiving the control signal and the error check signal, communicating a request to the host for an error-correcting re-transmission operation when an error exists in the received data, and communicating a request for an extending re-transmission operation when error does not exist in the received data.

Abstract: A method of communicating data between an external storage device and a USB host via a USB device is disclosed. The method includes receiving data from the USB host; and either (1) directly communicating the received data to the external storage device via an exclusive bus, or (2) indirectly communicating the received data to the external storage device via a USB bus, separate from the exclusive bus.

Abstract: A multi-chip package device includes first and second memory chips configured to share addresses and control signals. The first and second memory chips each include main memory, buffer memory, an option terminal for receiving an option voltage, an access signal generation block, and a controller. The main memory of the first memory chip stores boot code. The buffer memory of the first memory chip includes boot memory. The option voltages of the first and second memory chips have different voltage levels. The access signal generation block generates a buffer access signal that undergoes a one-way transition in response to the boot code address. The one-way transition of the buffer access signal of the first memory chip is a transition to activation, and the one-way transition of the buffer access signal of the second memory chip is a transition to inactivation.

Abstract: Disclosed is a method of performing a read operation in a NAND/RAM semiconductor memory device. The semiconductor memory device comprises a NAND flash memory device having a memory cell array and a page buffer, and a data RAM outputting data in response to a clock signal received from a host. The method comprising; sensing data stored in one page of the memory cell array in the page buffer, transferring the sensed data from the page buffer to the data RAM in multiple blocks via a corresponding number of transfer operations, and reading the transferred data from the data RAM in response to the host clock signal, wherein a read-out operation for the transferred data commences during any one of the plurality of transfer time periods.

Abstract: Terminal and method for transporting a still picture uses a moving picture terminal after extraction of a frame unit of still pictures, for example, from a moving picture. The extracted still picture frames can be encoded in a fixed quantizing value and stored before transmission, or the stored frame unit still pictures can be encoded in a fixed quantizing value using an overflow control technique or circuit. Further, the extracted still picture frame unit can be repeatedly sent using a varied quantizing value before transmission. Thus, the terminal and method for transporting a still picture permits transmission/reception of the still picture at a higher resolution than a moving picture regardless of time and place to enhance use of the moving picture terminal.

Abstract: A method for managing data stored in a non-volatile memory having a plurality of memory blocks includes, first, determining if an error occurs in the read data in a selected memory block. If an error occurs in the read data in the selected memory block, then a region to which the selected memory block belongs is determined. If the selected memory block belongs to a code data region, it is determined if the number of bit errors of the read data is less than or equal to an allowed number of bit errors. If number of bit errors of the read data is less than or equal to the allowed number of bit errors, the selected memory block of the code data region is replaced with a reserved memory block, and the selected memory block of the code data region is designated to a user data region.

Abstract: A video data coding/decoding apparatus includes: an encoder dividing a partition partitioned by a data partitioning technique into certain blocks, channel-coding the divided block data and transmitting a bit stream; and a decoder channel-decoding the bit stream received from the encoder so as to restore a video data. An error occurrence probability can be reduced by channel decoding the source-coded video data for each partition. In addition, by removing the marker emulation generated in the channel coding, a mobile image data of a better picture quality can be provided.

Abstract: A flash memory device comprises a non-volatile memory core operatively connected to first and second buffer memories through a page buffer. The device further comprises a first register adapted to receive command and address information from a host system, a copy circuit adapted to copy the command and address information from the first register to a second register within a control logic circuit. The device alternately transfers information to the first and second buffer memories during a cache read operation comprising a plurality of data read operations.

Abstract: In one aspect, a data processing system includes a OneNAND flash memory which includes an internal non-volatile memory and an internal buffer memory which temporarily stores a page data derived from the internal non-volatile memory, and a first memory controller which includes a speed-up buffer. The memory controller controls read operations of the OneNAND flash memory such that the page data stored in the OneNAND internal buffer memory is sequentially and continuously output in multiple data units from the OneNAND flash memory to an exterior device through the speed-up buffer.

Abstract: Disclosed is a method of performing a read operation in a NAND/RAM semiconductor memory device. The semiconductor memory device comprises a NAND flash memory device having a memory cell array and a page buffer, and a data RAM outputting data in response to a clock signal received from a host. The method comprising; sensing data stored in one page of the memory cell array in the page buffer, transferring the sensed data from the page buffer to the data RAM in multiple blocks via a corresponding number of transfer operations, and reading the transferred data from the data RAM in response to the host clock signal, wherein a read-out operation for the transferred data commences during any one of the plurality of transfer time periods.

Abstract: An oscillator circuit may include a latch circuit, a feed-back circuit, and an input circuit. The latch circuit may be configured to generate an oscillating output signal responsive to first and second input signals, and the feed-back circuit may be configured to generate first and second complementary feed-back signals responsive to the oscillating output signal from the latch circuit. The input circuit may be configured to generate the first and second input signals responsive to the first and second complementary feed-back signals. Related methods are also discussed.

Abstract: A memory may include first and second buffer memories and a memory core. The memory core may include memory blocks each having a plurality of pages and a page buffer for reading data from a selected memory block. A control logic may control the first and second buffer memories and the memory core. The control logic may have a register for storing address and command information of the memory core. The control logic may control the memory core so that data read periods for pages of the selected memory block are carried out according to the stored address and command information. The control logic may control the first and second buffer memories and the memory core so that data in the page buffer may be transferred to the first and/or second buffer memories during the data read periods.

Abstract: A flash memory device comprises a non-volatile memory core operatively connected to first and second buffer memories through a page buffer. The device further comprises a first register adapted to receive command and address information from a host system, a copy circuit adapted to copy the command and address information from the first register to a second register within a control logic circuit. The device alternately transfers information to the first and second buffer memories during a cache read operation comprising a plurality of data read operations.

Abstract: A multi-chip package device includes first and second memory chips configured to share addresses and control signals. The first and second memory chips each include main memory, buffer memory, an option terminal for receiving an option voltage, an access signal generation block, and a controller. The main memory of the first memory chip stores boot code. The buffer memory of the first memory chip includes boot memory. The option voltages of the first and second memory chips have different voltage levels. The access signal generation block generates a buffer access signal that undergoes a one-way transition in response to the boot code address. The one-way transition of the buffer access signal of the first memory chip is a transition to activation, and the one-way transition of the buffer access signal of the second memory chip is a transition to inactivation.

Abstract: A fuse-free circuit may include a NAND flash memory cell, and a switch to turn on or off in response to data stored in the NAND flash memory cell. The fuse-free circuit may be embodied in a semiconductor device that also includes an adjustable circuit coupled to the switch. The adjustable circuit may be structured to emulate the No_Cut or Cut operation of a fuse in response to the on or off state of the switch.

Abstract: A method for managing data stored in a non-volatile memory having a plurality of memory blocks includes, first, determining if an error occurs in the read data in a selected memory block. If an error occurs in the read data in the selected memory block, then a region to which the selected memory block belongs is determined. If the selected memory block belongs to a code data region, it is determined if the number of bit errors of the read data is less than or equal to an allowed number of bit errors. If number of bit errors of the read data is less than or equal to the allowed number of bit errors, the selected memory block of the code data region is replaced with a reserved memory block, and the selected memory block of the code data region is designated to a user data region.

Abstract: A memory system includes a flash memory device and an interface device. The flash memory device includes a one-time programmable block where protection data information is stored in a predetermined region, and the interface device includes a register for storing one-time programmable lock status information to indicate whether the one-time programmable block is programmed. When a program/erase command is applied externally in a one-time programmable mode, the interface device having the one-time programmable lock status information indicates whether the one-time programmable block is programmed. If the one-time programmable lock status information indicates that the one-time programmable block is programmed, the interface device cuts off an external access to the one-time programmable block.