Abstract: An apparatus and method for concealing defective pixels in image sensors having a test mode. The image sensing apparatus includes a sensing module for capturing an image from an object, wherein the sensing module includes a plurality of pixels and a light source for detecting a defect of the pixel and wherein the light source is turned on or off for a test mode; a controller for determining whether there are any detective pixels in an image frame received from the sensing module using the light source and for storing a position about defective pixels; and an image concealment unit for comparing a position of the detected defective pixels with a position of the image frame of the object and for concealing the detected defective pixels.

Abstract: Disclosed is an apparatus for converting an analog image data into a digital image data in a CMOS image sensor including a pixel array having M (row line)×N (column line) color pixels, wherein the color pixels include a first color pixel for sensing a first color, a second color pixel for sensing a second color and a third pixel for sensing a third color.

Abstract: An apparatus for panning and scaling a window in CMOS image sensor is described. The apparatus comprises a pixel array having a plurality of unit pixels, a row driving part, an analog-digital converting part, an address generating part for generating a row address and a column address for the panning and scaling, and a line buffering part for receiving the digital pixel data outputted from the analog-digital converting part and outputting a pixel data according to the column address. According to the apparatus, CMOS image sensor can directly extract a pixel data of a desired resolution and scale offset.

Abstract: The present invention provides a CMOS (Complementary Metal Oxide Semiconductor) image sensor including a unit pixel, wherein the unit pixel includes photodiodes for receiving incident light and for generating photo charges, single sensing node for selectively receiving the photo charges outputted from the photodiodes; a reset transistor for resetting the single sensing node; and a drive transistor for outputting electrical signals corresponding to voltage levels of the single sensing node, and wherein the CMOS image sensor samples the electrical signals through the correlated double sampling and then outputs a final image value to an external device.

Abstract: An apparatus and method for concealing defective pixels in image sensors having a test mode. The image sensing apparatus includes a sensing module for capturing an image from an object, wherein the sensing module includes a plurality of pixels and a light source for detecting a defect of the pixel and wherein the light source is turned on or off for a test mode; a controller for determining whether there are any detective pixels in an image frame received from the sensing module using the light source and for storing a position about defective pixels; and an image concealment unit for comparing a position of the detected defective pixels with a position of the image frame of the object and for concealing the detected defective pixels.

Abstract: A micro-controller unit for accessing external memory having different access time using a microcode. The micro-controller unit for accessing an external memory according to the characteristics of the external memory includes a first storage device for storing microcodes, a programmable memory for storing cycle extension data of a address latch enable signal and a wait signal and for selectively outputting the cycle extension data as an offset value to a microcode program counter in response to a sequence field from the first storage device and the microcode program counter for increasing a program counter value in response to the offset value from the programmable memory and for outputting an increased program counter value to the first storage device when the offset value is received from the programmable memory.

Abstract: A microprocessor has an external memory for storing data and includes an internal cache for storing program data to be executed and for generating a first flush signal; a prefetch queue for storing a series of instructions contained in the program; a decode block for decoding the instructions and for generating a second flush signal; a buffer; and a control block, in response to the first flush signal, for storing an address and a state of instructions to be flushed into the buffer and, in response to the first flush signal and a third flush signal from an external device, for generating a queue flush signal to thereby flush the prefetch queue.