Patents by Inventor Hyun-Geun Byun
Hyun-Geun Byun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8043869Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.Type: GrantFiled: October 29, 2010Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Yeong Cho, Yun-Seung Shin, Hyun-Geun Byun, Choong-Keun Kwak
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Patent number: 7994493Abstract: Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.Type: GrantFiled: August 21, 2008Date of Patent: August 9, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Yeong Cho, Du-Eung Kim, Yun-Seung Shin, Hyun-Geun Byun, Sang-Beom Kang, Beak-Hyung Cho, Choong-Keun Kwak
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Publication number: 20110053293Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.Type: ApplicationFiled: October 29, 2010Publication date: March 3, 2011Inventors: Woo-Yeong CHO, Yun-Seung Shin, Hyun-Geun Byun, Choong-Keun Kwak
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Patent number: 7851878Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.Type: GrantFiled: July 22, 2009Date of Patent: December 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Yeong Cho, Yun-Seung Shin, Hyun-Geun Byun, Choong-Keun Kwak
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Publication number: 20090273045Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.Type: ApplicationFiled: July 22, 2009Publication date: November 5, 2009Inventors: Woo-Yeong CHO, Yun-Seung SHIN, Hyun-Geun BYUN, Choong-Keun KWAK
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Patent number: 7582941Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.Type: GrantFiled: June 30, 2006Date of Patent: September 1, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Yeong Cho, Yun-Seung Shin, Hyun-Geun Byun, Choong-Keun Kwak
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Publication number: 20080303016Abstract: Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of pType: ApplicationFiled: August 21, 2008Publication date: December 11, 2008Inventors: Woo-Yeong Cho, Du-Eung Kim, Yun-Seung Shin, Hyun-Geun Byun, Sang-Beom Kang, Beak-Hyung Cho, Choong-Keun Kwak
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Patent number: 7427531Abstract: Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of pType: GrantFiled: December 30, 2005Date of Patent: September 23, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Yeong Cho, Du-Eung Kim, Yun-Seung Shin, Hyun-Geun Byun, Sang-Beom Kang, Beak-Hyung Cho, Choong-Keun Kwak
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Publication number: 20070047295Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.Type: ApplicationFiled: June 30, 2006Publication date: March 1, 2007Inventors: Woo-Yeong Cho, Yun-Seung Shin, Hyun-Geun Byun, Choong-Keun Kwak
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Patent number: 7151696Abstract: Integrated circuit memory devices include a first column of memory cells electrically coupled to a first pair of bit lines and a bit line precharge and selection circuit. This bit line precharge and selection circuit includes at least one stacked arrangement of thin-film transistors. These thin-film transistors include a first PMOS thin-film pull-up transistor and a first NMOS thin-film pass transistor. These thin-film transistors are electrically coupled to one of the first pair of bit lines. The first column of memory cells includes a column of TFT SRAM cells.Type: GrantFiled: January 24, 2005Date of Patent: December 19, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Ho Suh, Hyun-Geun Byun
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Publication number: 20060186483Abstract: Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of pType: ApplicationFiled: December 30, 2005Publication date: August 24, 2006Inventors: Woo-Yeong Cho, Du-Eung Kim, Yun-Seung Shin, Hyun-Geun Byun, Sang-Beom Kang, Beak-Hyung Cho, Choong-Keun Kwak
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Publication number: 20060062061Abstract: Integrated circuit memory devices include a first column of memory cells electrically coupled to a first pair of bit lines and a bit line precharge and selection circuit. This bit line precharge and selection circuit includes at least one stacked arrangement of thin-film transistors. These thin-film transistors include a first PMOS thin-film pull-up transistor and a first NMOS thin-film pass transistor. These thin-film transistors are electrically coupled to one of the first pair of bit lines. The first column of memory cells includes a column of TFT SRAM cells.Type: ApplicationFiled: January 24, 2005Publication date: March 23, 2006Inventors: Young-Ho Suh, Hyun-Geun Byun
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Patent number: 6594818Abstract: A generic wafer includes memory units separated by scribe lanes. Memory chips of different storage capacities can be produced from different numbers of memory units on the generic wafer by forming one or more interconnect layer specialized according to a desired storage capacity and cutting the wafer using a sawing pattern according to the desired storage capacity.Type: GrantFiled: March 21, 2001Date of Patent: July 15, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Su-Chul Kim, Hyun-Geun Byun, Kwang-Jin Lee, Jong-Cheol Lee, Uk-Rae Cho
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Publication number: 20020136046Abstract: A generic wafer includes memory units separated by scribe lanes. Memory chips of different storage capacities can be produced from different numbers of memory units on the generic wafer by forming one or more interconnect layer specialized according to a desired storage capacity and cutting the wafer using a sawing pattern according to the desired storage capacity.Type: ApplicationFiled: March 21, 2001Publication date: September 26, 2002Inventors: Su-Chui Kim, Hyun-Geun Byun, Kwang-Jin Lee, Jong-Cheol Lee, Uk-Rae Chio
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Patent number: 5754487Abstract: An SRAM, which includes a plurality of bit line pairs, a memory cell connected between each pair of the bit lines, and an address transition detection circuit for detecting transition of the externally applied address signal to generate a detection pulse signal, is provided with an improved bit line precharge circuit requiring only two transistors per bit line pair. The new precharge circuit is controlled by a bit line precharge control signal generator for generating a control signal determined by a ratio of impedances connected between a source voltage and ground voltage.Type: GrantFiled: November 13, 1996Date of Patent: May 19, 1998Assignee: Samsung Electronics Co., Ltd.Inventors: Du-Eung Kim, Choong-Keun Kwak, Young-Ho Suh, Hyun-Geun Byun