Abstract: A semiconductor memory device includes a bit line extending above a substrate in a second horizontal direction, first and second active patterns beneath the bit line, each of the first and second active patterns having a first surface in contact with the bit line without a dopant source layer therebetween and a second surface opposite to the first surface in a vertical direction, a back-gate electrode between the first and second active patterns and extending above the substrate in a first horizontal direction by crossing the bit line, a first word line extending in the first horizontal direction at one side of the first active pattern, a second word line extending in the first horizontal direction at an opposite side of the second active pattern, and contact patterns in contact with the second surfaces of the first and second active patterns.

Abstract: A semiconductor device includes a substrate including a cell array area and an interface area, bit lines on the cell array area and extending in a first horizontal direction, back gate lines on the bit lines and extending in a second direction, insulating blocks on the interface area and each overlapping the back gate lines in the second direction, word lines among which each pair of two adjacent word lines are on both sides of a corresponding back gate line, respectively, and extending on a sidewall of a corresponding insulating block, active semiconductor layers each between a corresponding back gate line and a corresponding word line on the cell array area and having one end electrically connected to a corresponding bit line, and a word line contact on the interface area and on a corresponding word line and a corresponding insulating block adjacent thereto.

Abstract: A semiconductor device includes a lower chip structure, and an upper chip structure on the lower chip structure. The lower chip structure includes a memory structure, a lower interconnection structure electrically connected to the memory structure, and a lower bonding pad electrically connected to the lower interconnection structure. The upper chip structure includes an upper base, a peripheral transistor on the upper base, a first upper interconnection structure electrically connected to the peripheral transistor, on the upper base, a through-via penetrating through the upper base and electrically connected to the first upper interconnection structure, an upper bonding pad bonded to the lower bonding pad, below the upper base, and an intermediate connection structure electrically connecting the upper bonding pad and the through-via, between the upper base and the lower chip.

Abstract: A semiconductor device includes a lower chip structure including a memory structure and a lower wiring structure connected to the memory structure and an upper chip structure on the lower chip structure, where the upper chip structure includes an upper base, peripheral transistors below the upper base, an intermediate wiring structure below the upper base and connected to the peripheral transistors, an upper wiring structure on the upper base, a first through-via penetrating the upper base between the upper wiring structure and the intermediate wiring structure, the first through-via connecting the upper wiring structure and the intermediate wiring structure, and a second through-via extending respectively downward and penetrating the upper base between the upper wiring structure and the lower wiring structure, the second through-via connecting the upper wiring structure and the lower wiring structure.

Abstract: A semiconductor device includes a lower substrate, a lower dielectric structure on the lower substrate, a transistor between the lower substrate and the lower dielectric structure, a lower bonding pad in the lower dielectric structure, an upper dielectric structure on the lower dielectric structure, an upper substrate on the upper dielectric structure, a memory cell structure between the upper substrate and the upper dielectric structure, and an upper bonding pad in the upper dielectric structure. A top surface of the lower bonding pad is in contact with a bottom surface of the upper bonding pad. The lower bonding pad and the upper bonding pad overlap the memory cell structure.

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a lower substrate, a lower dielectric structure on the lower substrate, a memory cell structure between the lower substrate and the lower dielectric structure, a lower bonding pad in the lower dielectric structure, an upper dielectric structure on the lower dielectric structure, an upper substrate on the upper dielectric structure, a transistor between the upper substrate and the upper dielectric structure, and an upper bonding pad in the upper dielectric structure. A top surface of the lower bonding pad is in contact with a bottom surface of the upper bonding pad. The lower bonding pad and the upper bonding pad overlap the memory cell structure.

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device includes a lower bonding structure that includes a lower substrate, a lower dielectric structure on the lower substrate, and a transistor between the lower substrate and the lower dielectric structure, an upper bonding structure that includes an upper dielectric structure on the lower dielectric structure, an upper substrate on the upper dielectric structure, and a memory cell structure between the upper substrate and the upper dielectric structure, a connection structure on the upper bonding structure, and a first through via that electrically connects the transistor to the memory cell structure. The transistor overlaps the memory cell structure. The first through via penetrates the upper substrate and the upper dielectric structure.

Abstract: A semiconductor device is provided. The semiconductor device includes: a lower structure including a bit line; a cell semiconductor body vertically overlapping the bit line, on the lower structure; a peripheral semiconductor body including a portion disposed on a same level as at least a portion of the cell semiconductor body, on the lower structure; and a peripheral gate on the peripheral semiconductor body, wherein the peripheral semiconductor body includes a lower region having a first width and an upper region having a second width, greater than the first width on the lower region.

Abstract: A semiconductor device may include a substrate, a bitline extending in a first direction on the substrate, and an active pattern on the bitline. The semiconductor device may include a back gate electrode extending beside one side of the active pattern in a second direction perpendicular to the first direction across the bitline, and a wordline extending in the second direction beside the other side of the active pattern. A length of the active pattern in the second direction may be greater than a length of the bitline in the second direction.

Abstract: A method of fabricating a semiconductor device may use, as an internal contact region, a region in which a memory cell region overlaps a core and/or peripheral region by bonding at least a partial region of the memory cell region to at least a partial region of the core and/or peripheral region by a direct bonding method, and thus, even when an additional contact region is secured outside the memory cell region to be smaller, signals and/or power may be transmitted between the memory cell region and the core and/or peripheral region.

Abstract: A semiconductor device includes bit line structures on a substrate. Each bit line structure extends in a second direction, and the bit line structures are spaced apart from each other in a first direction. The semiconductor device further includes semiconductor patterns spaced apart from each other in the second direction on each of the bit line structures, insulating interlayer patterns between neighboring ones of the semiconductor patterns in the first direction, and word lines spaced apart from each other in the second direction on the bit line structures. Each word line extends in the first direction adjacent to the semiconductor patterns. The semiconductor device further includes capacitors disposed on and electrically connected to the semiconductor patterns, respectively. A seam extending in the second direction is formed in each of the insulating interlayer patterns.

Abstract: A semiconductor device may include a substrate including a memory cell region between a first connection region and a second connection region, gate electrodes extending in a first direction and including first pad regions having a step structure on the first connection region, back gate electrodes between the gate electrodes and extending in a direction opposite the first direction, vertical conductive patterns extending in a vertical direction and spaced apart from each other in the first direction on the memory cell region of the substrate, and active layers between the gate electrodes and the back gate electrodes on the memory cell region of the substrate. The active layers may extend in a second direction, intersecting the first direction, and may be electrically connected to the vertical conductive patterns. The back gate electrodes may include second pad regions having a step structure on the second connection region.

Abstract: A semiconductor memory device may include a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, and a stack including word lines and interlayer insulating patterns, which are alternatingly stacked in a third direction perpendicular to the first direction and the second direction, the stack having a staircase structure on the second region. The word lines may extend from the first region to the second region in the first direction. Each of the word lines may include sub-gate electrodes, which extend parallel to each other in the first region, and a word line pad, which is connected in common to the sub-gate electrodes in the second region.

Abstract: A semiconductor memory device may include a peripheral circuit structure including peripheral circuits integrated on a semiconductor substrate in a first region and a first keypad disposed in a second region; a stack provided on the first region of the peripheral circuit structure, the stack including a plurality of first conductive lines extending in a first direction and are vertically stacked; an upper insulating layer covering the stack; an interconnection layer provided on the upper insulating layer; a penetration plug spaced apart from the stack and is provided to penetrate the upper insulating layer to connect the interconnection layer to the peripheral circuits of the peripheral circuit structure; a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; and a penetration structure provided to penetrate the molding structure and vertically overlap with the first keypad.

Abstract: A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.

Abstract: A semiconductor memory device including a transistor body extending in a first horizontal direction and including a first source/drain region, a single-crystal channel layer, and a second source/drain region sequentially arranged in the first horizontal direction, a gate electrode layer extending in a second horizontal direction orthogonal to the first horizontal direction and covering upper and lower surfaces of the single-crystal channel layer, a bit line connected to the first source/drain region, extending in a vertical direction, and having a first width in the second horizontal direction, a spacer covering upper and lower surfaces of the first source/drain region and having a second width greater than the first width, and a cell capacitor on a side opposite to the bit line with respect to the transistor body in the first horizontal direction and including lower and upper electrode layers and a capacitor dielectric layer therebetween may be provided.

Abstract: A semiconductor memory device includes a word line extended parallel to a top surface of a semiconductor substrate, a channel pattern crossing the word line and having a long axis parallel to the top surface, a bit line extended perpendicular to the top surface and in contact with a first side surface of the channel pattern, and a data storage element in contact with a second side surface of the channel pattern opposite to the first side surface. The channel pattern includes a first dopant region adjacent to the bit line, a second dopant region adjacent to the data storage element, and a channel region between the first and second dopant regions and overlapped with the word line. At least one of the first and second dopant regions includes a low concentration region adjacent to the channel region, and a high concentration region spaced apart from the channel region.

Abstract: A semiconductor memory device may include a cell array structure including first bonding pads, which are electrically connected to memory cells, and a peripheral circuit structure including second bonding pads, which are electrically connected to peripheral circuits and are bonded to the first bonding pads. The cell array structure may include a stack including horizontal conductive patterns stacked in a vertical direction, a vertical structure including vertical conductive patterns , which are provided to cross the stack in the vertical direction, and a power capacitor provided in a planarization insulating layer covering a portion of the stack.

Abstract: Semiconductor memory devices may include a cell array structure that may include a memory cell array including three-dimensionally arranged memory cells and first bonding pads connected to the memory cell array and a peripheral circuit structure that may include peripheral circuits and second bonding pads bonded to the first bonding pads. The cell array structure may include a lower dielectric layer having a first surface and a second surface opposite to the first surface, a stack structure including horizontal electrodes stacked in a vertical direction on the first surface of the lower dielectric layer, a vertical structure including vertical conductive patterns that extend in the vertical direction and cross the horizontal electrodes, and an input/output pad on the second surface of the lower dielectric layer.

Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.