Patents by Inventor Hyun-Gi Kim

Hyun-Gi Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250080509
    Abstract: A method of encrypting data, performed by a computer system includes: dividing transmission target data into an arbitrary number of blocks; selecting an encryption key generation target block to be used for extracting an encryption key from among the plurality of divided blocks; generating an encryption key based on the encryption key generation target block; selecting an encryption target block from among remaining blocks excluding the encryption key generation target block; and encrypting the encryption target block based on the generated encryption key.
    Type: Application
    Filed: October 31, 2022
    Publication date: March 6, 2025
    Inventors: Young Hu KIM, Nam Kyu KIM, Yong Man JEONG, Hyun Su KIM, Hyun Gi KIM
  • Publication number: 20230248263
    Abstract: Provided are a method, apparatus and system for prediction of a neonatal brain development prognosis. The computing device includes a memory; and at least one processor performing communication with the memory, wherein the processor is configured to extract cerebral blood flow (CBF) and brain tissue relaxation times T1 and T2 from the input magnetic resonance imaging (MRI) of a subject newborn; generate brain neurodevelopment prediction data of the subject newborn using a pregenerated brain neurodevelopment prediction model; and control the output of the generated brain neurodevelopment prediction data of the subject newborn.
    Type: Application
    Filed: December 27, 2022
    Publication date: August 10, 2023
    Applicants: THE CATHOLIC UNIVERSITY OF KOREA INDUSTRY-ACADEMIC COOPERATION FOUNDATION, AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Hyun Gi KIM, Jang Hoon LEE
  • Publication number: 20230071794
    Abstract: A method for constructing a lane level map using a three-dimensional point cloud map is provided. According to the method, during scan matching for estimating the location of a vehicle in the process of automatically constructing a 3D high-definition map, the amount of computation is reduced by reducing the size of a target 3D map. Thereby the method is performed fast and accurate position estimation. In addition, even if the position estimation by scan matching fails, more robust position estimation is possible by estimating the location of the vehicle using LiDAR odometry performed in parallel. The method builds and merges a precise lane map with a pre-built 3D point cloud map using such robust localization to build a more precise 3D precise map and a lane node-link map. By using these three-dimensional precise maps and maps that generate node-links in lanes, a more effective route planning algorithm that can be provided.
    Type: Application
    Filed: May 30, 2022
    Publication date: March 9, 2023
    Inventors: Hyun Chul SHIM, Dae Gyu Lee, Hyun Gi Kim
  • Patent number: 11557332
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: January 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
  • Publication number: 20210272623
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Sang-Uhn CHA, Hyun-Gi KIM, Hoon SIN, Ye-Sin RYU, In-Woo JUN
  • Patent number: 11031065
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
  • Publication number: 20210005247
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Inventors: Sang-Uhn CHA, Hyun-Gi KIM, Hoon SIN, Ye-Sin RYU, In-Woo JUN
  • Patent number: 10811078
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
  • Patent number: 10802912
    Abstract: Disclosed are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a memory cell array having a plurality of memory cells and includes an error correcting code (ECC) decoder configured to receive first data and a first parity for the first data from selected memory cells of the memory cell array, generate a second parity for the first data using an H-matrix and the first data, compare the first parity to the second parity to generate a first syndrome, and generate a decoding status flag (DSF) with different states on the basis of a number of “0” or “1” bits included in the first syndrome.
    Type: Grant
    Filed: April 6, 2019
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Uhn Cha, Hyun Gi Kim
  • Patent number: 10692397
    Abstract: A smart nasometer according to an embodiment of the present invention includes: a hardware unit worn on a head of a user for measuring nasal and oral sounds and providing feedback for the user; and a computational unit for receiving and processing speech signals of the nasal and oral sounds measured by the hardware unit, wherein the hardware unit includes: a microphone unit for separately measuring the nasal and oral sounds in a non-touched state of the user's philtrum, wherein the computational unit includes: a nasalance adjustment unit for adjusting a nasalance of the nasal and oral sounds measured by the microphone unit.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: June 23, 2020
    Assignees: POSTECH ACADEMY-INDUSTRY FOUNDATION, INDUSTRIAL COOPERATION FOUNDATION OF CHONBUK NATIONAL UNIVERSITY, CHONBUK NATIONAL UNIVERSITY HOSPITAL
    Inventors: Heecheon You, Myoung-Hwan Ko, Jong-Kwan Park, Younggeun Choi, Hyun Gi Kim, Han Soo Lee, Gradiyan Budi Pratama, Min-Jung Yu, Ki Wook Kim, Yun Ju Jo, Jin Kook Lee
  • Publication number: 20200168269
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 28, 2020
    Inventors: Sang-Uhn CHA, Hyun-Gi KIM, Hoon SIN, Ye-Sin RYU, In-Woo JUN
  • Publication number: 20200159617
    Abstract: Disclosed are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a memory cell array having a plurality of memory cells and includes an error correcting code (ECC) decoder configured to receive first data and a first parity for the first data from selected memory cells of the memory cell array, generate a second parity for the first data using an H-matrix and the first data, compare the first parity to the second parity to generate a first syndrome, and generate a decoding status flag (DSF) with different states on the basis of a number of “0” or “1” bits included in the first syndrome.
    Type: Application
    Filed: April 6, 2019
    Publication date: May 21, 2020
    Inventors: Sang Uhn CHA, Hyun Gi KIM
  • Patent number: 10586584
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
  • Publication number: 20190371391
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Application
    Filed: December 20, 2018
    Publication date: December 5, 2019
    Inventors: Sang-Uhn CHA, Hyun-Gi KIM, Hoon SIN, Ye-Sin RYU, In-Woo JUN
  • Patent number: 9953985
    Abstract: A method of manufacturing an integrated circuit device includes forming multilayered stack structures that extend parallel to and separated from one another on a substrate, followed by forming a buried conductive layer including a plurality of conductive line patterns that extend parallel to an extending direction of the multilayered stack structures and alternate with the multilayered stack structures; removing portions of the buried conductive layer to thereby separate the plurality of conductive line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the extending direction of the multilayered stack structures; and forming a plurality of insulating fences that fill the plurality of insulating fence spaces and include a plurality of insulating line patterns extending parallel to one another.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-gi Kim, Sang-moo Jeong, Seon-ju Kim, Hye-won Kim
  • Publication number: 20180061272
    Abstract: A smart nasometer according to an embodiment of the present invention includes: a hardware unit for mesmartasuring and feedbacking nasal and oral sounds worn by the user; and a computational unit for receiving a speech signal measured by the hardware unit and performing processing, wherein the hardware unit includes: a microphone unit for separating and measuring the nasal and oral speech signals in a non-touched state of the user's philtrum, wherein the operation unit includes: a nasalance adjustment unit for adjusting a nasalance of the speech signal measured by the microphone unit.
    Type: Application
    Filed: August 25, 2017
    Publication date: March 1, 2018
    Inventors: Heecheon YOU, Myoung-Hwan KO, Jong-Kwan PARK, Younggeun CHOI, Hyun Gi KIM, Han Soo LEE, Gradiyan Budi PRATAMA, Min-Jung YU
  • Publication number: 20180012894
    Abstract: A method of manufacturing an integrated circuit device includes forming multilayered stack structures that extend parallel to and separated from one another on a substrate, followed by forming a buried conductive layer including a plurality of conductive line patterns that extend parallel to an extending direction of the multilayered stack structures and alternate with the multilayered stack structures; removing portions of the buried conductive layer to thereby separate the plurality of conductive line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the extending direction of the multilayered stack structures; and forming a plurality of insulating fences that fill the plurality of insulating fence spaces and include a plurality of insulating line patterns extending parallel to one another.
    Type: Application
    Filed: June 21, 2017
    Publication date: January 11, 2018
    Inventors: Hyun-gi KIM, Sang-moo JEONG, Seon-ju KIM, Hye-won KIM
  • Patent number: 9184091
    Abstract: First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bo-Young Song, Cheol-Ju Yun, Seung-Hee Ko, Jina Kim, Hyun-Gi Kim, Chae-Ho Lim
  • Patent number: 8946077
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeon-Kyu Lee, Bo-Young Song, Seung-Hee Ko, Jin-A Kim, Hyun-Gi Kim, Cheol-Ju Yun, Chae-Ho Lim
  • Publication number: 20140231892
    Abstract: First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.
    Type: Application
    Filed: December 10, 2013
    Publication date: August 21, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Bo-Young SONG, Cheol-Ju YUN, Seung-Hee KO, Jina KIM, Hyun-Gi KIM, Chae-Ho LIM