Abstract: An exemplary embodiment of the present disclosure provides a separator for a fuel cell, which is stacked on a reaction layer including a membrane electrode assembly (MEA). The separator includes a plate body stacked on the reaction layer, a wave pattern provided on one surface of the plate body that faces the reaction layer, the wave pattern being configured to define a reaction channel disposed between the reaction layer and the plate body and provided in a first direction in which a reactant gas is supplied, so that the reactant gas flows along the reaction channel, and a land provided along a lateral end of the wave pattern and disposed to be in contact with the reaction layer, thereby obtaining an advantageous effect of improving performance and operational efficiency.

Abstract: An embodiment solid electrolyte includes a first compound and a second compound. The first compound is represented by a first chemical formula Li7-aPS6-a(X11-bX2b)a, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, and wherein 0<a?2 and 0<b<1, and the second compound is represented by a second chemical formula Li7-cP1-2dMdS6-c-3d(X11-eX2e)c, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, wherein M represents Ge, Si, Sn, or any combination thereof, and wherein 0<c?2, 0<d<0.5, and 0<e<1.

Abstract: A pellicle for extreme ultraviolet (EUV) lithography is based on yttrium carbide and used in a EUV lithography process. The pellicle for EUV lithography includes a pellicle layer that has a core layer containing yttrium carbide. The yttrium carbide is YCx in which the atomic percentage of carbon is within a range of 25% to 45%.

Abstract: A display device includes a via insulating layer on a substrate; a first electrode on the via insulating layer; a pixel defining layer including an inclined region on the first electrode and including a first opening exposing a portion of the first electrode, and a flat region at a side of the inclined region and in contact with the via insulating layer; a light emitting layer on the portion of the first electrode exposed by the first opening; organic particles on the flat region of the pixel defining layer; an encapsulation layer covering the pixel defining layer, the light emitting layer, and the organic particles, and including a first layer, a second layer, and a third layer; and a first light blocking layer on the third layer of the encapsulation layer to overlap the flat region of the pixel defining layer and form a second opening.

Abstract: Provided are a method, apparatus and system for prediction of a neonatal brain development prognosis. The computing device includes a memory; and at least one processor performing communication with the memory, wherein the processor is configured to extract cerebral blood flow (CBF) and brain tissue relaxation times T1 and T2 from the input magnetic resonance imaging (MRI) of a subject newborn; generate brain neurodevelopment prediction data of the subject newborn using a pregenerated brain neurodevelopment prediction model; and control the output of the generated brain neurodevelopment prediction data of the subject newborn.

Abstract: A method for constructing a lane level map using a three-dimensional point cloud map is provided. According to the method, during scan matching for estimating the location of a vehicle in the process of automatically constructing a 3D high-definition map, the amount of computation is reduced by reducing the size of a target 3D map. Thereby the method is performed fast and accurate position estimation. In addition, even if the position estimation by scan matching fails, more robust position estimation is possible by estimating the location of the vehicle using LiDAR odometry performed in parallel. The method builds and merges a precise lane map with a pre-built 3D point cloud map using such robust localization to build a more precise 3D precise map and a lane node-link map. By using these three-dimensional precise maps and maps that generate node-links in lanes, a more effective route planning algorithm that can be provided.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

Abstract: Disclosed are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a memory cell array having a plurality of memory cells and includes an error correcting code (ECC) decoder configured to receive first data and a first parity for the first data from selected memory cells of the memory cell array, generate a second parity for the first data using an H-matrix and the first data, compare the first parity to the second parity to generate a first syndrome, and generate a decoding status flag (DSF) with different states on the basis of a number of “0” or “1” bits included in the first syndrome.

Abstract: A smart nasometer according to an embodiment of the present invention includes: a hardware unit worn on a head of a user for measuring nasal and oral sounds and providing feedback for the user; and a computational unit for receiving and processing speech signals of the nasal and oral sounds measured by the hardware unit, wherein the hardware unit includes: a microphone unit for separately measuring the nasal and oral sounds in a non-touched state of the user's philtrum, wherein the computational unit includes: a nasalance adjustment unit for adjusting a nasalance of the nasal and oral sounds measured by the microphone unit.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

Abstract: Disclosed are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a memory cell array having a plurality of memory cells and includes an error correcting code (ECC) decoder configured to receive first data and a first parity for the first data from selected memory cells of the memory cell array, generate a second parity for the first data using an H-matrix and the first data, compare the first parity to the second parity to generate a first syndrome, and generate a decoding status flag (DSF) with different states on the basis of a number of “0” or “1” bits included in the first syndrome.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

Abstract: A method of manufacturing an integrated circuit device includes forming multilayered stack structures that extend parallel to and separated from one another on a substrate, followed by forming a buried conductive layer including a plurality of conductive line patterns that extend parallel to an extending direction of the multilayered stack structures and alternate with the multilayered stack structures; removing portions of the buried conductive layer to thereby separate the plurality of conductive line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the extending direction of the multilayered stack structures; and forming a plurality of insulating fences that fill the plurality of insulating fence spaces and include a plurality of insulating line patterns extending parallel to one another.

Abstract: A smart nasometer according to an embodiment of the present invention includes: a hardware unit for mesmartasuring and feedbacking nasal and oral sounds worn by the user; and a computational unit for receiving a speech signal measured by the hardware unit and performing processing, wherein the hardware unit includes: a microphone unit for separating and measuring the nasal and oral speech signals in a non-touched state of the user's philtrum, wherein the operation unit includes: a nasalance adjustment unit for adjusting a nasalance of the speech signal measured by the microphone unit.

Abstract: A method of manufacturing an integrated circuit device includes forming multilayered stack structures that extend parallel to and separated from one another on a substrate, followed by forming a buried conductive layer including a plurality of conductive line patterns that extend parallel to an extending direction of the multilayered stack structures and alternate with the multilayered stack structures; removing portions of the buried conductive layer to thereby separate the plurality of conductive line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the extending direction of the multilayered stack structures; and forming a plurality of insulating fences that fill the plurality of insulating fence spaces and include a plurality of insulating line patterns extending parallel to one another.