Patents by Inventor HYUN-GON PYO

HYUN-GON PYO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11348938
    Abstract: In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: May 31, 2022
    Inventors: Il-Woo Kim, Sang-Gi An, Hyun-Gon Pyo, Ik-Soo Kim, Hee-Sook Park, Ji-Woon Im
  • Publication number: 20200199752
    Abstract: A baffle including a base plate disposed in a central portion of a showerhead in an apparatus for processing a substrate. An extension plate is movably connected to a planar surface of the base plate. The extension plate is configured to extend and contract radially from the base plate to change a diameter of the baffle.
    Type: Application
    Filed: July 15, 2019
    Publication date: June 25, 2020
    Inventors: MIN-JOON KIM, MYOUNG-WOON KIM, HEE-JONG JEONG, IL-WOO KIM, JAE-HOON PARK, JI-WOON IM, HYUN-GON PYO
  • Publication number: 20200168628
    Abstract: In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.
    Type: Application
    Filed: June 19, 2019
    Publication date: May 28, 2020
    Inventors: IL-WOO KIM, SANG-GI AN, HYUN-GON PYO, IK-SOO KIM, HEE-SOOK PARK, JI-WOON IM