Patents by Inventor Hyun-Hak JUNG
Hyun-Hak JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10103117Abstract: Provided is a method of manufacturing a fan-out type wafer level package. The method includes forming a fiducial mark pattern on a frame, attaching a semiconductor die to the frame with respect to the fiducial mark pattern, encapsulating the semiconductor die with a passivation layer, for reconstituting the semiconductor die as a wafer level, and sequentially forming a metal seed layer, a redistribution layer, an under bump metal (UBM) seed layer, an UBM layer, and a solder ball on a bonding pad of the semiconductor die upward exposed by an opening region of the passivation layer to finish a fan-out type wafer level package.Type: GrantFiled: August 24, 2016Date of Patent: October 16, 2018Assignee: SFA Semicon Co., Ltd.Inventors: Hyun Hak Jung, Eun Dong Kim, Jong Won Lee, Jai Kyoung Choi, Byeong Ho Jeong
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Patent number: 10050499Abstract: Provided is a method of manufacturing a voice coil, and more particularly, a method of manufacturing a voice coil in which a coil pattern is formed on a wafer level package. The method includes (a) forming a first coil pattern including a first area in which a first seed metal layer is exposed upward, a second area in which a first passivation layer for forming a via hole in the first area is formed, and a third area in which a first photoresist layer is formed in a portion of the first area and the second area on an upper surface of a wafer, (b) filling an inside of the via hole formed in the first coil pattern with a conductive material and forming first coil windings, and (c) removing the first photoresist layer formed in the third area.Type: GrantFiled: November 13, 2015Date of Patent: August 14, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jai Kyoung Choi, Eun Dong Kim, Hyun Hak Jung, Hyeong Min Kim, Jong Hwi Jung, Su Kyung Lim
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Patent number: 9935072Abstract: The present disclosure provides a semiconductor package that prevents a bump bridge from being formed between adjacent conductive bumps to realize a fine bump pitch when each unit circuit part is directly stacked without using a printed circuit board and a method for manufacturing the same. The semiconductor package includes a first semiconductor chip structure including a first unit circuit part, a first passivation layer disposed on the first unit circuit part, and a conductive bump electrically connected to the first unit circuit part, and a second semiconductor chip structure including a second unit circuit part, a second passivation layer having a stepped portion that is recessed inward and disposed on the second unit circuit part, and a bump pad provided in the stepped portion. The first semiconductor chip structure and the second semiconductor chip structure are stacked to allow the conductive bump to be bonded to the bump pad within the stepped portion.Type: GrantFiled: October 11, 2016Date of Patent: April 3, 2018Assignee: SFA SEMICON CO., LTD.Inventors: Byeong Ho Jeong, Eun Dong Kim, Jong Won Lee, Hyun Hak Jung, Jai Kyoung Choi
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Publication number: 20170125369Abstract: The present disclosure provides a semiconductor package that prevents a bump bridge from being formed between adjacent conductive bumps to realize a fine bump pitch when each unit circuit part is directly stacked without using a printed circuit board and a method for manufacturing the same. The semiconductor package includes a first semiconductor chip structure including a first unit circuit part, a first passivation layer disposed on the first unit circuit part, and a conductive bump electrically connected to the first unit circuit part, and a second semiconductor chip structure including a second unit circuit part, a second passivation layer having a stepped portion that is recessed inward and disposed on the second unit circuit part, and a bump pad provided in the stepped portion. The first semiconductor chip structure and the second semiconductor chip structure are stacked to allow the conductive bump to be bonded to the bump pad within the stepped portion.Type: ApplicationFiled: October 11, 2016Publication date: May 4, 2017Inventors: Byeong Ho JEONG, Eun Dong KIM, Jong Won LEE, Hyun Hak JUNG, Jai Kyoung CHOI
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Publication number: 20170062368Abstract: Provided is a method of manufacturing a fan-out type wafer level package. The method includes forming a fiducial mark pattern on a frame, attaching a semiconductor die to the frame with respect to the fiducial mark pattern, encapsulating the semiconductor die with a passivation layer, for reconstituting the semiconductor die as a wafer level, and sequentially forming a metal seed layer, a redistribution layer, an under bump metal (UBM) seed layer, an UBM layer, and a solder ball on a bonding pad of the semiconductor die upward exposed by an opening region of the passivation layer to finish a fan-out type wafer level package.Type: ApplicationFiled: August 24, 2016Publication date: March 2, 2017Inventors: Hyun Hak JUNG, Eun Dong KIM, Jong Won LEE, Jai Kyoung CHOI, Byeong Ho JEONG
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Publication number: 20170047831Abstract: Provided is a method of manufacturing a voice coil, and more particularly, a method of manufacturing a voice coil in which a coil pattern is formed on a wafer level package. The method includes (a) forming a first coil pattern including a first area in which a first seed metal layer is exposed upward, a second area in which a first passivation layer for forming a via hole in the first area is formed, and a third area in which a first photoresist layer is formed in a portion of the first area and the second area on an upper surface of a wafer, (b) filling an inside of the via hole formed in the first coil pattern with a conductive material and forming first coil windings, and (c) removing the first photoresist layer formed in the third area.Type: ApplicationFiled: November 13, 2015Publication date: February 16, 2017Applicant: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.Inventors: Jai Kyoung CHOI, Eun Dong KIM, Hyun Hak JUNG, Hyeong Min KIM, Jong Hwi JUNG, Su Kyung LIM
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Publication number: 20160365195Abstract: Provided is a method for manufacturing a voice coil, and more particularly, to a voice coil manufacturing method for forming a coil pattern on a wafer level package. The method for manufacturing a voice coil includes forming a first passivation layer on an upper surface of a wafer, forming a first coil directly on the first passivation layer, forming a second passivation layer on the first passivation layer and on an upper surface of the first coil, forming a third passivation layer on an upper surface of the second passivation layer, forming a second coil directly on the third passivation layer, and forming an external connection terminal on a portion of the second coil.Type: ApplicationFiled: July 9, 2015Publication date: December 15, 2016Inventors: Jai Kyoung CHOI, Eun Dong KIM, Hyun Hak JUNG, Hyeong Min KIM, Su Kyung LIM
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Patent number: 9466586Abstract: Provided are a semiconductor package and a method for manufacturing a semiconductor package. The method for manufacturing a wafer-level fan-out package includes attaching semiconductor chips sawed to have a predetermined size to one surface of a wafer at predetermined intervals, forming a first passivation layer on surfaces of the semiconductor chips and the wafer, forming a redistribution layer electrically connected to the semiconductor chips on portions of an upper surface of the first passivation layer, forming a second passivation layer on the upper surface of the first passivation layer and surfaces of portions of the redistribution layer, forming external connection terminals on portions of the redistribution layer in which the second passivation layer has not been formed, and performing sawing along package boundary lines (sawing lines) and polishing the wafer to be removed such that lower surfaces of the semiconductor chips are exposed.Type: GrantFiled: July 8, 2015Date of Patent: October 11, 2016Assignee: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.Inventors: Jai Kyoung Choi, Eun Dong Kim, Hyun Hak Jung, Hyeong Min Kim, Su Kyung Lim
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Patent number: 9349667Abstract: A method of manufacturing a stacked package includes a first process of stacking a semiconductor chip on an upper surface of a PCB having a wiring pattern and a via-hole pad, a second process of forming a photoresist (PR) layer on the upper surface of the PCB having the semiconductor chip and the via-hole pad, a third process of removing the photoresist layer of a remaining region except for an upper portion of the via-hole pad so that a photoresist layer of a via-hole region remains only at the upper portion of the via-hole pad, a fourth process of forming a molding layer by molding the upper surface of the PCB having the semiconductor chip to expose an upper surface of the photoresist layer of the via-hole region, and a fifth process of removing the photoresist layer of the via-hole region to form a via-hole on the via-hole pad.Type: GrantFiled: April 17, 2014Date of Patent: May 24, 2016Assignee: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.Inventors: Jae Bok Yoo, Hyun Hak Jung, Kyoung Min Song
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Patent number: 9347806Abstract: Disclosed is a sensor having an embedded electrode, which can be manufactured at a reduced cost and applied to many different fields. The sensor comprises: a sensing stack in which a first conductive layer and a second conductive layer are stacked and layered with a separation layer interposed therebetween; and an electrode terminal arranged at a side surface of the sensing stack and electrically connected to the first and second conductive layers. The first and second conductive layers are exposed on at least one side surface of the sensing stack except for the side surface on which the electrode terminal is arranged, to thereby form a sensing surface.Type: GrantFiled: September 24, 2013Date of Patent: May 24, 2016Assignees: Joinset Co., Ltd., Expantech Co., Ltd.Inventors: Sun-Ki Kim, Sung-Youl Kim, Hyun-Hak Jung, Jung-Suk Kim
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Publication number: 20150228507Abstract: A method of manufacturing a stacked package includes a first process of stacking a semiconductor chip on an upper surface of a PCB having a wiring pattern and a via-hole pad, a second process of forming a photoresist (PR) layer on the upper surface of the PCB having the semiconductor chip and the via-hole pad, a third process of removing the photoresist layer of a remaining region except for an upper portion of the via-hole pad so that a photoresist layer of a via-hole region remains only at the upper portion of the via-hole pad, a fourth process of forming a molding layer by molding the upper surface of the PCB having the semiconductor chip to expose an upper surface of the photoresist layer of the via-hole region, and a fifth process of removing the photoresist layer of the via-hole region to form a via-hole on the via-hole pad.Type: ApplicationFiled: April 17, 2014Publication date: August 13, 2015Applicant: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.Inventors: Jae Bok YOO, Hyun Hak JUNG, Kyoung Min SONG
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Publication number: 20140041464Abstract: Disclosed is a sensor having an embedded electrode, which can be manufactured at a reduced cost and applied to many different fields. The sensor comprises: a sensing stack in which a first conductive layer and a second conductive layer are stacked and layered with a separation layer interposed therebetween; and an electrode terminal arranged at a side surface of the sensing stack and electrically connected to the first and second conductive layers. The first and second conductive layers are exposed on at least one side surface of the sensing stack except for the side surface on which the electrode terminal is arranged, to thereby form a sensing surface.Type: ApplicationFiled: September 24, 2013Publication date: February 13, 2014Applicants: EXPANTECH CO., LTD., JOINSET CO., LTD.Inventors: Sun-Ki KIM, Sung-Youl KIM, Hyun-Hak JUNG, Jung-Suk KIM