Abstract: A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-decoder electrically connected to the plurality of inter-decoders and disposed between the plurality of inter-decoders. A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-drivers electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-driver electrically connected to the plurality of inter-drivers, and disposed between the plurality of inter-drivers.

Abstract: A memory device includes a stacked resistive memory cell array comprising a plurality of resistive memory cell layers stacked on a semiconductor substrate, wherein respective memory cell layers are configured to store data according to respective program modes comprising a number of bits per cell. The memory device further includes a control circuit configured to identify a program mode of a selected memory cell layer responsive to an address signal and to access the selected memory cell layer responsive to the address signal according to the identified program mode. The program modes may include a single-level cell mode and at least one multi-level cell mode.

Abstract: A bi-directional resistive memory device includes a memory cell array including a plurality of memory cells and an input/output (I/O) circuit. The I/O circuit is configured to generate a first voltage having a positive polarity and a second voltage having a negative polarity, provide one of the first voltage and the second voltage to the memory cell array through a bitline responsive to a logic state of input data, and adjust magnitudes of the first and second voltage when data written in the memory cell array has an offset. Related memory systems and methods are also provided.

Abstract: A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit.

Abstract: A memory device includes an array of resistance change memory cells divided into a first memory block including a first selected memory cell of a first plurality of memory cells and a second memory block including a second selected memory cell of a second plurality of memory cells, and sensing and writing circuitry configured to simultaneously activate a line connected with the first and second selected memory cells. The first and second selected memory cells may be written by iteratively applying a level-controlled write signal to memory cells not having a programmed state equal to the write data until a verify-read operation indicates respective programmed states for the first and second selected memory cells are equal to the write data.

Abstract: To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc.

Abstract: A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage.

Abstract: In a memory device and in a method for controlling a memory device, the memory device comprises a magnetic structure that stores information in a plurality of domains of the magnetic structure. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure. A position detector unit compares the information read by a read current from the read unit from multiple domains of the plurality of domains of the magnetic structure to identify the presence of an expected information pattern at select domains of the plurality of domains.

Abstract: A memory device is comprised of a magnetic structure that stores information in a plurality of domains of the magnetic structure. A write unit writes information to at least one of the plurality of domains of the magnetic structure by applying a write current to the magnetic structure in response to a control signal. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure in response to the control signal. A domain wall movement control unit is coupled to a portion of the magnetic structure and moves information stored in the plurality of domains in the magnetic structure to other domains in the magnetic structure in response to the control signal. The write unit, the read unit and the domain wall movement control unit are all coupled to the same control signal line that provides the control signal.

Abstract: A memory device architecture includes N arrays respectively for storing a 1/N of a page and N write/read circuits, where N is a natural number, respectively for writing or reading a 1/N of the page to/from each of the N arrays.

Abstract: A semiconductor device, a semiconductor system including the same, and a voltage supply method of the semiconductor device are provided. The semiconductor device includes at least two semiconductor memory devices and a voltage supply controller configured to selectively supply a voltage to each of the at least two semiconductor memory devices.

Abstract: A semiconductor device having an architecture for reducing an area is provided. The semiconductor device includes a memory cell array including a plurality of non-volatile memory cells, a plurality of registers each configured to store pre-fetch unit data, and a write driver circuit configured to write pre-fetch unit data sequentially output from the plurality of registers to the memory cell array during a write operation. The semiconductor device also includes a sense amplifier circuit configured to sense and amplify pre-fetch unit data sequentially output from the memory cell array and to sequentially store the amplified pre-fetch unit data in the plurality of registers, respectively, during a read operation.

Abstract: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

Abstract: A cognitive radio communication terminal including a transmission processing unit to divide data by a quiet time slot that is allocated at a first point in time of a collision detection period, to transmit at least one portion of the divided data to a reception side, and a sensing unit to determine whether at least one of a feature information and an energy of another terminal is detected in a channel with the reception side during the quiet time slot of the first point in time. Where neither the feature information nor the energy of the other terminal is detected based on a determination of the sensing unit, the transmission processing unit transmits the remaining divided data.

Abstract: A cognitive radio base station may transmit, for each channel, common control channel information to a plurality of cognitive radio terminals at different points in time, respectively. Accordingly, the cognitive radio base station may receive a channel allocation request from the plurality of cognitive radio terminals receiving the common control channel information and allocate a plurality of channels to the plurality of cognitive radio terminals, respectively, to perform communication. In response to another terminal existing in a corresponding channel, the cognitive radio base station may update the common control channel information and switch to another channel to transmit subsequent common control channel information at, for example, a closest point in time to thereby broadcast the updated common control channel information to the plurality of cognitive radio terminals using the switched channel.

Abstract: A cognitive radio communication device including at least two radio frequency chains is provided. In order to perform a feature detection, the cognitive radio frequency device may reduce or eliminate a quiet time where a data communication is suspended using the at least two RF chains. While one RF chain performs the feature detection, another RF chain may perform the data communication.

Abstract: The present invention provides a novel phenylpropionic acid derivative and a PPAR-? modulator comprising the same as an active ingredient. The phenylpropionic acid derivative of the present invention has modulatory action on function of PPAR-? and then exhibits hypoglycemic, hypolipidemic and insulin resistance-reducing effects on PPAR-mediated diseases or disorders. Therefore, the present invention is prophylactically or therapeutically effective for diabetes and metabolic diseases.

Abstract: A method of writing multi-bit data to a semiconductor memory device with memory cells storing data defined by a threshold value, the method comprising, for each memory cell, writing a least significant bit, verifying completion of writing the least significant bit, verifying including comparing a written value to one of a low least significant bit verification value and a high least significant bit verification value, and writing a next significant bit upon completion of writing the least significant bit.

Abstract: A low density parity code (LDPC) encoding and decoding devices and encoding and decoding methods thereof are provided. An LDPC encoding device includes an information obtaining unit which obtains status information of at least two frequency bands, a matrix generation unit which generates a parity check matrix based on the status information, the parity check matrix including sub matrices which correspond to the at least two frequency bands, and an encoder which generates data bits and parity bits using an LDPC with the generated parity check matrix.

Abstract: A cognitive radio communication system using a multiple input multiple output (MIMO) communication technology is provided. A cognitive radio base station includes a plurality of antennas, a group setting unit to set at least one sensing terminal group that includes at least one sensing terminal among a plurality of terminals, and a signal generator to generate a transmission signal to transmit the transmission signal using channels formed between the plurality antennas and the plurality of terminals, so that the at least one sensing terminal is accorded a sensing time.