Abstract: A radio frequency switch may include: a common port transmitting and receiving a radio frequency signal; a receive switch unit including a first switch unit having a plurality of first switch elements and a second switch unit having a plurality of second switch elements; and a transmit switch unit including a third switch unit having a plurality of third switch elements and a fourth switch unit having a plurality of fourth switch elements. The receive switch unit may further include a plurality of first capacitors connected between a first terminal and a body terminal of each of the plurality of first switch elements. The transmit switch unit may further include a plurality of second capacitors connected between a second terminal and a body terminal of each of the plurality of third switch elements.

Abstract: A radio frequency switch may include: a common port transmitting and receiving a radio frequency signal; a receive switch unit including a first switch unit having a plurality of first switch elements and a second switch unit having a plurality of second switch elements; and a transmit switch unit including a third switch unit having a plurality of third switch elements and a fourth switch unit having a plurality of fourth switch elements. The receive switch unit may further include a plurality of first capacitors connected between a first terminal and a body terminal of each of the plurality of first switch elements. The transmit switch unit may further include a plurality of second capacitors connected between a second terminal and a body terminal of each of the plurality of third switch elements.

Abstract: A radio frequency (RF) switching circuit may include: a first switching circuit unit connected between a first signal port for signal transmission and reception and a common connection node connected to an antenna port and operated according to a first gate signal; a second switching circuit unit connected between a second signal port for signal transmission and reception and the common connection node and operated according to a second gate signal; a negative voltage generating unit generating a negative voltage using a voltage of an RF signal from the common connection node; and a gate signal generating unit generating the first and second gate signals using the negative voltage from the negative voltage generating unit and an operating voltage.

Abstract: A radio frequency (RF) switch may include: a common port; a first switching unit; and a second switching unit. The first switching unit further includes a third switching device having one end coupled to a body of one of the plurality of first switching devices and the other end coupled to a first ground terminal, and the second switching unit further includes a fourth switching device having one end coupled to a body of one of the plurality of second switching devices and the other end coupled to a second ground terminal.

Abstract: A RF switch may include: a common port coupled to an antenna to transmit and receive first and second high frequency signals; a transmitting switching unit coupled between a transmitting port transferring the first high frequency signal and the common port and including a plurality of switching devices coupled to each other in series; and a receiving switching unit coupled between a receiving port transferring the second high frequency signal and the common port and including a first switching unit including a first switching device. The first switching unit may further include a second switching device having a first terminal coupled to a first terminal of the first switching device and a second terminal coupled to a control terminal of the first switching device.

Abstract: A radio frequency switching circuit may include a first switching circuit unit including first to nth (n is a natural number greater than at least 2) transistors M1 to Mn connected in series between a first signal port for transmission and reception of signals and a common connection node connected to an antenna port and operated according to a first gate signal; a second switching circuit unit connected in series between the common connection node and a second signal port for transmission and reception of signals and operated according to a second gate signal; and a first impedance adjuster forming an alternating current (AC) ground path between a ground and a gate of the first transistor of the first switching circuit unit when the first switching circuit unit is in an off-state.

Abstract: Disclosed herein is a circuit for preventing an element from being damaged although output impedance of a final transistor is changed in a power amplifier. The power amplifier includes: a power stage amplifying a signal; a transformer connected to an output terminal of the power stage and coupling a signal output from the power stage; and a controller controlling a bias voltage from the power stage according to the coupled signal. Although output impedance is changed, damage to the power amplifier can be prevented. Also, the power amplifier can be automatically controlled to maintain performance thereof by sensing an operational state in which output impedance is normal.

Abstract: There is provided a digitally controlled oscillator. The digitally controlled oscillator includes a resonance circuit unit generating a resonance signal according to an equivalent capacitance formed by a parallel connection between a first capacitance varied depending on a digital control code and a second capacitance varied depending on an inverted digital control code generated by inverting the digital control code, and preset inductance; and an oscillation circuit unit providing negative resistance to the resonance circuit unit and forming oscillation conditions in the resonance circuit unit.

Abstract: The present invention includes: a temperature compensation circuit for generating a digital signal corresponding to a temperature of a transistor and outputting a compensation bias current obtained by adding a control current to a reference bias current or by subtracting the control signal from the reference bias current using the generated digital signal; a characteristics compensation circuit for detecting a characteristics error of a mirror transistor connected to the transistor in parallel and for outputting a compensation signal to compensate the characteristics error; and a bias compensation circuit for compensating a bias power applied to the transistor using the compensation bias current and the compensation signal to output the compensated bias power. The present invention is capable of improving the performance of the transistor.

Abstract: There is provided a DC offset cancellation circuit including: a capacitor circuit unit including at least one capacitor connected between an input terminal and an input of an amplifier; a MOSFET circuit unit including a plurality of MOSFETs connected in series between a first connection node connected to a predetermined one of both terminals of the capacitor circuit unit and a ground and operating in a linear region; and a switching circuit unit including a plurality of switch elements for selecting several MOSFETs previously selected from among the plurality of MOSFETs of the MOSFET circuit unit, respectively.

Abstract: The present invention includes: a temperature compensation circuit for generating a digital signal corresponding to a temperature of a transistor and outputting a compensation bias current obtained by adding a control current to a reference bias current or by subtracting the control signal from the reference bias current using the generated digital signal; a characteristics compensation circuit for detecting a characteristics error of a mirror transistor connected to the transistor in parallel and for outputting a compensation signal to compensate the characteristics error; and a bias compensation circuit for compensating a bias power applied to the transistor using the compensation bias current and the compensation signal to output the compensated bias power. The present invention is capable of improving the performance of the transistor.

Abstract: Disclosed is a CMOS power amplifier. A temperature compensation circuit of a CMOS power amplifier may include: a bias circuit unit supplying a gate bias voltage to a power amplification circuit part; a bias detection unit determining a class type of the power amplification circuit part according to the gate bias voltage; a temperature detection unit detecting a temperature-proportional voltage in proportion to ambient temperature; a temperature compensation control unit generating a compensation control value according to the temperature-proportion voltage in the class type determined by the bias detection unit; and a conversion unit converting the compensation control value of the temperature compensation control unit into a linear bias control value and providing the linear bias control value to the bias circuit unit, wherein the bias circuit unit compensates the gate bias voltage according to the linear bias control value of the conversion unit.

Abstract: There is provided a power amplifier that can maintain a constant gain by detecting a level of a signal being input and a level of a signal being output. A power amplifier according to an aspect of the invention may include: an amplification section having at least one amplification unit amplifying an input signal according to an adjustable gain to thereby output the amplified input signal; a detection section detecting signal levels of an input signal and an output signal of the amplification section; and a gain maintaining section controlling a bias power according to a detection result of the detection section so that a gain of the amplification section is maintained within a predetermined gain range.

Abstract: Disclosed is a CMOS power amplifier. A temperature compensation circuit of a CMOS power amplifier may include: a bias circuit unit supplying a gate bias voltage to a power amplification circuit part; a bias detection unit determining a class type of the power amplification circuit part according to the gate bias voltage; a temperature detection unit detecting a temperature-proportional voltage in proportion to ambient temperature; a temperature compensation control unit generating a compensation control value according to the temperature-proportion voltage in the class type determined by the bias detection unit; and a conversion unit converting the compensation control value of the temperature compensation control unit into a linear bias control value and providing the linear bias control value to the bias circuit unit, wherein the bias circuit unit compensates the gate bias voltage according to the linear bias control value of the conversion unit.

Abstract: A received signal strength indicator according to an aspect of the invention may include a gain calibration section including a calibration limiter, a calibration load unit and a comparison and adjustment unit. The calibration load unit is connected to output terminals of the calibration limiter, and generating an output differential voltage whose gain is a unit gain when a predetermined input differential voltage is input to the calibration limiter, and a comparison and adjustment unit comparing the input differential voltage with the output differential voltage, and adjusting an output of a variable current source included in the calibration limiter so that the input differential voltage becomes identical to the output differential voltage.

Abstract: There is provided a power amplifier that can maintain a constant gain by detecting a level of a signal being input and a level of a signal being output. A power amplifier according to an aspect of the invention may include: an amplification section having at least one amplification unit amplifying an input signal according to an adjustable gain to thereby output the amplified input signal; a detection section detecting signal levels of an input signal and an output signal of the amplification section; and a gain maintaining section controlling a bias power according to a detection result of the detection section so that a gain of the amplification section is maintained within a predetermined gain range.

Abstract: The present invention relates to an exponential function generator which is realized with only CMOS element without BJT element, not limited by the physical properties of the element or a square circuit, and not complicated in its configuration, and a variable gain amplifier using the same. The exponential function generator includes a voltage-current converter, 1st to nth curve generators for mirroring the current from the voltage-current converter, outputting a current adjusted according to a predetermined ratio, and an output end for outputting the sum of the current from the 1st to nth curve generators. The exponential current generator is configured to generate the current exponentially adjusted according to the control voltage.

Abstract: A received signal strength indicator according to an aspect of the invention may include a gain calibration section including a calibration limiter, a calibration load unit and a comparison and adjustment unit. The calibration load unit is connected to output terminals of the calibration limiter, and generating an output differential voltage whose gain is a unit gain when a predetermined input differential voltage is input to the calibration limiter, and a comparison and adjustment unit comparing the input differential voltage with the output differential voltage, and adjusting an output of a variable current source included in the calibration limiter so that the input differential voltage becomes identical to the output differential voltage.

Abstract: Disclosed herein is a digital automatic fine tuning method and apparatus, which is capable of detecting a difference between a nominal frequency and an intermediate frequency generated in a tuner using a counter, and applying the counted data of the counter as a fine tuning value for the intermediate frequency without using a decoder by controlling the reset and preset operations of the counter that counts the frequency of the intermediate frequency.

Abstract: Disclosed herein is a digital automatic fine tuning method and apparatus, which is capable of detecting a difference between a nominal frequency and an intermediate frequency generated in a tuner using a counter, and applying the counted data of the counter as a fine tuning value for the intermediate frequency without using a decoder by controlling the reset and preset operations of the counter that counts the frequency of the intermediate frequency.