Patents by Inventor Hyun Im

Hyun Im has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130323868
    Abstract: A deposition apparatus includes: a deposition source including a spray nozzle linearly arranged in a first direction and discharging a deposition material; and a pair of angle control members disposed at both sides of the deposition source and controlling a discharging direction angle of the deposition material. Each angle control member includes a rotation axis parallel to the first direction, and a plurality of shielding plates inst7lled about the rotation axis and separated from each other by a predetermined interval around the rotation axis. Although the deposition angle is changed according to the increasing of the process time, the deposition angle is compensated to form a uniform thin film. Also, the organic thin film may be uniformly deposited through each pixel of an organic light emitting diode (OLED) display, thereby increasing luminance uniformity for each pixel.
    Type: Application
    Filed: November 1, 2012
    Publication date: December 5, 2013
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ja-Hyun Im, Kwan-Hee Lee, Ji-Hwan Yoon, Joong-Won Sim, Tae-Kwang Sung
  • Publication number: 20130302966
    Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
  • Patent number: 8569945
    Abstract: An organic light emitting device and a method of fabricating the same are disclosed. The organic light emitting device includes an anode and a cathode that comprises a magnesium-calcium layer. An organic layer having at least an organic emission layer is interposed between the anode and the cathode. The organic light emitting device may have reduced driving voltage characteristics, increased luminous efficiency characteristics, and improved lifespan characteristics without forming a separate electron injection layer because of the excellent electron injection characteristics.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: October 29, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kwan-Hee Lee, Ja-Hyun Im
  • Patent number: 8558348
    Abstract: A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyuhwan Oh, Dong-Hyun Im, Soonoh Park, Dongho Ahn, Young-Lim Park, Eun-Hee Cho
  • Publication number: 20130228753
    Abstract: An organic light-emitting diode (OLED).
    Type: Application
    Filed: August 29, 2012
    Publication date: September 5, 2013
    Inventors: Jung-Min Moon, Ja-Hyun Im, Tae-Jin Park
  • Patent number: 8507353
    Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 13, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
  • Patent number: 8502184
    Abstract: A nonvolatile memory device and a method of fabricating the same are provided. The nonvolatile memory device includes a conductive pillar that extends from a substrate in a first direction, a variable resistor that surrounds the conductive pillar, a switching material layer that surrounds the variable resistor, a first conductive layer that extends in a second direction, and a first electrode that extends in a third direction and contacts the first conductive layer and the switching material layer. Not one of the first, second, and third directions is parallel to another one of the first, second, and third directions.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeong-Geun An, Sung-Lae Cho, Ik-Soo Kim, Dong-Hyun Im, Eun-Hee Cho
  • Publication number: 20130112949
    Abstract: An organic light-emitting device including: a substrate; a first electrode; a second electrode; an emission layer between the first electrode and the second electrode; and an electron transport layer between the emission layer and the second electrode, wherein the emission layer includes a blue emission layer, the electron transport layer includes a unit that includes a first single layer including a first material, a first mixed layer on the first single layer and including the first material and a second material, a second single layer on the first mixed layer and including the second material, a second mixed layer on the second single layer and including the first and second materials, and a third single layer on the second mixed layer and including the first material, wherein the first mixed layer has a thickness that is larger than that of the second mixed layer.
    Type: Application
    Filed: July 6, 2012
    Publication date: May 9, 2013
    Inventors: Joong-Won Sim, Kwan-Hee Lee, Ji-Hwan Yoon, Ja-Hyun Im
  • Publication number: 20130109148
    Abstract: In a method of forming a pattern, a first mask layer and a first sacrificial layer may be sequentially formed on an object layer. The first sacrificial layer may be partially etched to form a first sacrificial layer pattern. A second sacrificial layer pattern may be formed on the first mask layer. The second sacrificial layer pattern may enclose a sidewall of the first sacrificial layer pattern. The first sacrificial layer pattern may then be removed. The first mask layer may be partially etched using the second sacrificial layer pattern as an etching mask to form a first mask layer pattern. The object layer may be partially etched using the first mask layer pattern as an etching mask.
    Type: Application
    Filed: August 22, 2012
    Publication date: May 2, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyu-Hwan OH, Seung-Pil KO, Byeung-Chul KIM, Youn-Seon KANG, Jae-Joo SHIM, Dong-Hyun IM, Doo-Hwan PARK, Ki-Seok SUH
  • Patent number: 8387961
    Abstract: A vacuum chuck comprises a main body including a support projection and a vacuum groove arranged in a lattice form on the top surface thereof, an installation space, a vacuum space, a filter space. The main body further includes an inlet that communicates with the installation space and an outlet that communicates with the vacuum space. An air saving valve B, a vacuum sensor S, a vacuum generator V and a filter F are installed in the installation space, vacuum space and filter space of the main body. A pressure gauge and a vacuum gauge that are mounted on the front side and communicate with the inlet and the vacuum space respectively. A main body cover that is air-tightly coupled to the lower part of the main body, and a filter cover that is air-tightly coupled to the lower part of the filter space.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: March 5, 2013
    Inventor: Kwon-Hyun Im
  • Publication number: 20120326110
    Abstract: A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 27, 2012
    Inventors: Gyu-Hwan OH, Byoung-Jae Bae, Dong-Hyun Im, Doo-Hwan Park
  • Publication number: 20120313844
    Abstract: An organic light-emitting display device includes a substrate, a plurality of pixel electrodes arranged in a matrix on the substrate, and an organic common layer covering the pixel electrodes. The pixel electrodes include a plurality of first pixel electrodes, a plurality of second pixel electrodes, and a plurality of third pixel electrodes. An n-th pixel column includes the second pixel electrodes and the third pixel electrodes arranged alternately, an (n+1)-th pixel column which is adjacent to the n-th pixel column includes the first pixel electrodes, and an (n+2)-th pixel column which is adjacent to the (n+1)-th pixel column includes the second pixel electrodes and the third pixel electrodes arranged alternately, wherein n is a natural number. One of the second and third pixel electrodes is disposed in the n-th pixel column in a row and the other one of the second and third pixel electrodes is disposed in the (n+2)-th pixel column in the same row.
    Type: Application
    Filed: May 21, 2012
    Publication date: December 13, 2012
    Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.
    Inventors: Ja-Hyun Im, Kwan-Hee Lee, Beom-Seok Kim
  • Publication number: 20120305884
    Abstract: A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern.
    Type: Application
    Filed: August 13, 2012
    Publication date: December 6, 2012
    Inventors: Gyuhwan Oh, Dong-Hyun Im, Soonoh Park, Dongho Ahn, Young-Lim Park, Eun-Hee Cho
  • Publication number: 20120295368
    Abstract: Kits for detecting a target material and methods of detecting a target material by using the kits are provided, the kits include a target material binding portion including a first molecule and a probe linked to the first molecule, and a target material detection portion including a plurality of nanoparticles each having a surface to which a compound having a zwitterion and a second molecule are linked. The first molecule is specifically bound to the second molecule in a pair.
    Type: Application
    Filed: March 27, 2012
    Publication date: November 22, 2012
    Applicants: POSTECH ACADEMY-INDUSTRY FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu-hyun Im, No-kyoung Park, Jong-jin Park, Jae-hyun Hur, Joon-hyuck Park, Sung-jee Kim
  • Publication number: 20120289019
    Abstract: In a method of forming a pattern, a plurality of first line patterns and first spacers filling spaces between the adjacent first line patterns are formed on an object layer. The first line patterns and the first spacers extend in a first direction. A plurality of second line patterns are formed on the first line patterns and the first spacers. The second line patterns extend in a second direction substantially perpendicular to the first direction. The first spacers are partially removed by a wet etching process. The object layer is etched using the first and second line patterns as an etching mask.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 15, 2012
    Inventors: Dong-Hyun Im, Byoung-Jae Bae, Young-Jae Kim, Dae-Keun Kang
  • Publication number: 20120282751
    Abstract: A method of fabricating an integrated circuit device includes forming first and second patterns extending in first and second directions, respectively, on a target layer. The first patterns comprise a metal oxide and/or metal silicate material having an etch selectivity with respect to that of the target layer. The second patterns comprise a material having an etch selectivity with respect to those of the first patterns and the target layer. The target layer is selectively etched using the first patterns and the second patterns as an etch mask to define holes respectively extending through the target layer to expose a layer therebelow. At least one of the first and second patterns is formed using respective mask patterns formed by a photolithographic process, and the at least one of the first and second patterns have a finer pitch than that of the respective mask patterns.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 8, 2012
    Inventors: Gyu-hwan OH, Doo-hwan Park, Dong-hyun Im, Kyung-min Chung
  • Publication number: 20120279762
    Abstract: A method of forming a stretchable conductive pattern includes forming a base substrate; forming a plurality of non-linear trench lines that include peaks and valleys arranged at constant intervals in the base substrate; forming a polymer-metal precursor mixture pattern by filling the trench lines with a mixture of the polymer-metal precursor; converting the polymer-metal precursor mixture of the polymer-metal precursor mixture pattern into a polymer gel/metal nano-particle complex to form a polymer gel/metal nano-particle complex pattern; and primarily transferring the polymer gel/metal nano-particle complex pattern in the base substrate onto an acceptor base substrate.
    Type: Application
    Filed: April 27, 2012
    Publication date: November 8, 2012
    Applicants: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-hyun HUR, Jong-jin PARK, Kyu-hyun IM, Un-yong JEONG, Min-woo PARK, Dong-choon HYUN
  • Publication number: 20120252187
    Abstract: A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other , forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.
    Type: Application
    Filed: March 16, 2012
    Publication date: October 4, 2012
    Inventors: Gyu-Hwan Oh, Dong-Hyun Kim, Kyung-Min Chung, Dong-Hyun Im
  • Publication number: 20120251824
    Abstract: Example embodiments relate to stretchable conductive nanofibers including at least one stretchable nanofiber and a conductive layer on a structure of the stretchable nanofiber. The conductive layer may include carbon nanotubes and metal nanoparticles on the surface of the stretchable nanofiber. The carbon nanotubes and metal nanoparticles may form a percolation network. The stretchable nanofiber includes stretchable polymers.
    Type: Application
    Filed: November 16, 2011
    Publication date: October 4, 2012
    Applicants: Industry-Academic Cooperation Foundation, Yonsei University, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-hyun Hur, Jong-jin Park, Kyu-hyun Im, Un-yong Jeong, Min-woo Park
  • Patent number: 8278206
    Abstract: A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: October 2, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyuhwan Oh, Dong-Hyun Im, Soonoh Park, Dongho Ahn, Young-Lim Park, Eun-Hee Cho