Abstract: The present invention relates to a composition containing a bean extract extracted by low-concentration, low-grade alcohol or fractions thereof. The composition exhibits excellent effects in improving blood circulation, improving obesity, and preventing diabetes, hyperlipidemia and the like, and exhibits the effects of alleviating or treating the symptoms of diabetes, hyperlipidemia, and the like. The present invention also relates to a method for improving blood circulation and vascular health.

Abstract: In an embodiment, there is provided a method of creating a package, the method comprising: providing an initial substrate, wherein the initial substrate comprises a carrier foil, a functional copper foil, and an interface release layer between the carrier foil and the functional copper foil; building up copper portions on the functional copper foil; attaching a chip to a first copper portion; coupling the chip to a second copper portion; encapsulating at least the chip and the copper portions with a mold; and removing the carrier foil and interface release layer.

Abstract: In an embodiment, there is provided a method of creating a package, the method comprising: providing an initial substrate, wherein the initial substrate comprises a carrier foil, a functional copper foil, and an interface release layer between the carrier foil and the functional copper foil; building up copper portions on the functional copper foil; attaching a chip to a first copper portion; coupling the chip to a second copper portion; encapsulating at least the chip and the copper portions with a mold; and removing the carrier foil and interface release layer.

Abstract: A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will track the power supply voltage and the difference between the power supply voltage and the charge reservoir voltage will be maintained substantially constant over a predefined power supply range. The voltage regulator includes a bandgap reference generator, a first differential circuit for producing a transition voltage from the reference voltage and the power supply voltage, a first transistor for comparing the power supply voltage with the boost voltage, a second transistor for comparing the transition voltage with the reference voltage and a latching comparator for equating the signal outputs from the first and second transistors so as to define a control signal for the on-chip voltage generator.

Abstract: A pull-down circuit for a TTL compatible data output buffer uses NMOS devices. The pull-down circuit comprising two NMOS stages. Namely, a diode configuration stage where the gate and drain electrodes are shorted together during pull-down and a common-source stage. Both PMOS and NMOS devices are used for shorting the gate and drain electrodes.

Abstract: A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will track the power supply voltage and the difference between the power supply voltage and the charge reservoir voltage will be maintained substantially constant over a predefined power supply range. The voltage regulator includes a bandgap reference generator, a first differential circuit for producing a transition voltage from the reference voltage and the power supply voltage, a first transistor for comparing the power supply voltage with the boost voltage, a second transistor for comparing the transition voltage with the reference voltage and a latching comparator for equating the signal outputs from the first and second transistors so as to define a control signal for the on-chip voltage generator.

Abstract: High speed, low power signal switching logic implementable in bipolar or BiCMOS technology is described. Signal switching is between a first prescribed state and a second prescribed state and is accomplished using a conventional active signal pull-up circuit in combination with a novel self-biased, feedback-controlled active signal pull-down circuit. The active signal pull-down circuit is driven by a feedback signal obtained from the active pull-up circuitry such that only a single input connection to the signal switching circuit is required. Preferably, the active signal pull-up circuit comprises an emitter follower coupled transistor and the drive signal for the active signal pull-down circuit is taken from the collector thereof via a dc-coupling level shifter. Various signal switching circuit embodiments are described.

Abstract: A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in the accessed cells. Such an arrangement eliminates the need for a reference voltage generator since the precharge voltage is not the same voltage for each RAS cycle.

Abstract: A dual port SRAM is shown which comprises first and second word lines and first and second bit lines. A pair of semiconductor memory devices are cross coupled into a bistable circuit for storing true and complement logic levels and are coupled between common and power supply lines. A first access semiconductor is connected between the first bit line and one semiconductor memory device, and its control electrode is connected to the first word line. A second access semiconductor is connected between the second bit line and another of the semiconductor memory devices, and its control electrode is connected to the second word line. A write circuit is provided for applying write potentials to the first bit and word lines to switch the conduction states of the semiconductor memory devices.

Abstract: A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will track the power supply voltage and the difference between the power supply voltage and the charge reservoir voltage will be maintained substantially constant over a predefined power supply range. The voltage regulator includes a bandgap reference generator, a first differential circuit for producing a transition voltage from the reference voltage and the power supply voltage, a first transistor for comparing the power supply voltage with the boost voltage, a second transistor for comparing the transition voltage with the reference voltage and a latching comparator for equating the signal outputs from the first and second transistors so as to define a control signal for the on-chip voltage generator.

Abstract: A breather pipe with a leakage checking device for a container which allows air in the container to be ventilated when the mobile container transports high viscosity liquid such as engine fuel of automobiles normally, and on the other hand closes up the breather pipe to prevent a leakage of the liquid when the moving container is accelerated, decelerated or turned rapidly, or inclined or overturned. The breather pipe comprises a pipe member having a lower part which is vertically mounted on an opening formed at an upper surface of the container and an upper part which is curved downwardly. The pipe member also has an upper throat and regularly circumferentially spaced lower depressions formed at the circumferential surface thereof, and a spherical float positioned in the pipe member between the upper throat and the lower depressions.

Abstract: Novel boosted power supplies are disclosed for an internal, on-chip regulator circuit which includes a differential amplifier coupler to a series regulating element operating as a source follower, and in which a voltage pump circuit is provided to generate a boosted power supply for the differential amplifier. The voltage pump preferably includes a ring oscillator for supplying pulses for the voltage pump. The new on-chip voltage regulators are designed for n-well CMOS technology circuits, and can be applied to BiCMOS as well as n-well CMOS circuits. The new circuits utilize voltage boosting techniques to increase the potential at the gate of the series regulating element operating as a source follower, and also improve the power supply rejection. Furthermore, these circuits preferably use clamping diodes to limit negative voltage swings at the gate of the series regulating element and to improve the settling time of the voltage regulator circuit.

Abstract: Output driver circuits which do not require two stacked PMOS pull-up transistors in order to interface a lower on-chip supply voltage with a higher voltage off-chip bus provide a significant savings in chip area for DRAMs. According to a first embodiment, an on-chip pump circuit generates the necessary voltage to interface to the external bus. A second embodiment detects and compares the external bus voltage to the on-chip V.sub.DD during tri-state. The higher voltage between the bus and V.sub.DD is used to control the PMOS pull-up device properly. A third embodiment is a hybrid of the first and second embodiments. The external bus is compared to V.sub.DD as in the second embodiment, but a higher-than-V.sub.DD voltage is generated on-chip as in the first embodiment. This on-chip generated voltage is used to control the PMOS pull-up device instead of the bus voltage when the bus voltage is higher than V.sub.DD.

Abstract: A high speed multiplexer circuit is described which includes a plurality of input bipolar transistors and a reference bipolar transistor. The input and reference transistors have their emitters commonly coupled to an emitter current supply and their collectors coupled to a collector supply. The collector of the reference transistor is coupled to the collector supply through an impedance. A reference potential is connected to the base of the reference bipolar transistor and biases it for conduction. An input signal to be multiplexed is connected to the base of each of the input bipolar transistors and a diode circuit is coupled between the base of each of the input bipolar transistors and a switch input. A switch input, in a first state, causes the diode circuit to conduct and clamp the base of an input transistor, to prevent it from responding to a signal input.

Abstract: An ECL circuit having an output circuit with improved pull-down characteristics. An active pull-down circuit is provided by a p-channel JFET which includes a back gate connection or a merged p-channel JFET/NPN device. The gate and/or back gate are switched, providing a lowering of the device impedance during switching of the device from pull-up to pull-down operation, resulting in an improved pull-down speed.

Abstract: Circuitry for implementing a gate enhanced lateral transistor to provide a circuit having a bipolar current driving capability and an FET channel voltage drop. The circuits provide switching of the lateral transistor by enabling both gate and base connections. The device is merged into an FET providing essentially no voltage drop across the collector-emitter connections permitting the collector to reach a full power supply voltage.