Abstract: A display driving circuit includes a buffer section, an N-dot switch circuit, a charge sharing switch circuit, and a sharing voltage level control switch circuit. The buffer section buffers a plurality of pixel driving signals outputted from a plurality of DACs. The N-dot switch circuit selects paths of the plurality of pixel driving signals outputted from the buffer section in response to a first path selecting signal or a second path selecting signal that is determined depending upon a dot inversion method, and switches the paths to a plurality of output terminals. The charge sharing switch circuit shares charges among the plurality of output terminals in response to a charge sharing control signal. The sharing voltage level control switch circuit controls charge sharing between the plurality of output terminals and a voltage level upon charge sharing, in response to a sharing voltage level control signal.

Abstract: An amplifier and a display driving circuit. The amplifier includes an input stage, a bias stage and an output stage. The input stage determines voltage levels of two nodes in correspondence to two input voltages received in response to a first bias voltage, and includes four path selecting switches, two input transistors and one bias transistor. The bias stage generates two class AB output voltages which correspond to the voltage levels of the two nodes, and includes current mirrors, ten path selecting switches, class AB bias circuits and two bias transistors. The output stage generates an output voltage VOUT that corresponds to the two class AB output voltages, and includes two coupling capacitors and two push-pull transistors. The plurality of path selecting switches operate by one signal of a first path selecting signal and a second path selecting signal that are exclusively enabled with respect to each other.

Abstract: A display driving circuit and method is capable of minimizing the residual image of a display panel as well as consumption electric current. The display driving circuit generates driving signals corresponding to valid data and black data and transmits the driving signals to a display panel, and includes N data selection switches (where N is the integer), N buffers, N buffer output selection switches, and multiple charge sharing switches. The N data selection switches select one of the valid data and the black data. The N buffers buffer the signal selected by the respective data selection switches. The N buffer output selection switches switch outputs of the buffers to output the respective driving signals. The multiple charge sharing switches connect the neighboring pairs of the driving signals.

Abstract: A power management IC includes a first IC having a boost converter IC which generates a second voltage using a first voltage supplied from an outside and supplies the second voltages to a charge pump, a reference voltage generation circuit, and an EEPROM; and a second IC configured to be inputted with a third voltage and a fourth voltage as outputs of the charge pump and output a fifth voltage and a sixth voltage. The second IC has a voltage regulator which regulates the third voltage and the fourth voltage or the fifth voltage and the sixth voltage and generates an eighth voltage and a ninth voltage as voltages required for programming operation or erasing operation of the EEPROM.

Abstract: An amplifier and a display driving circuit. The amplifier includes an input stage, a bias stage and an output stage. The input stage determines voltage levels of two nodes in correspondence to two input voltages received in response to a first bias voltage, and includes four path selecting switches, two input transistors and one bias transistor. The bias stage generates two class AB output voltages which correspond to the voltage levels of the two nodes, and includes current mirrors, ten path selecting switches, class AB bias circuits and two bias transistors. The output stage generates an output voltage VOUT that corresponds to the two class AB output voltages, and includes two coupling capacitors and two push-pull transistors. The plurality of path selecting switches operate by one signal of a first path selecting signal and a second path selecting signal that are exclusively enabled with respect to each other.

Abstract: A display driving circuit and method is capable of minimizing the residual image of a display panel as well as consumption electric current. The display driving circuit generates driving signals corresponding to valid data and black data and transmits the driving signals to a display panel, and includes N data selection switches (where N is the integer), N buffers, N buffer output selection switches, and multiple charge sharing switches. The N data selection switches select one of the valid data and the black data. The N buffers buffer the signal selected by the respective data selection switches. The N buffer output selection switches switch outputs of the buffers to output the respective driving signals. The multiple charge sharing switches connect the neighboring pairs of the driving signals.

Abstract: A display driving circuit includes a buffer section, an N-dot switch circuit, a charge sharing switch circuit, and a sharing voltage level control switch circuit. The buffer section buffers a plurality of pixel driving signals outputted from a plurality of DACs. The N-dot switch circuit selects paths of the plurality of pixel driving signals outputted from the buffer section in response to a first path selecting signal or a second path selecting signal that is determined depending upon a dot inversion method, and switches the paths to a plurality of output terminals. The charge sharing switch circuit shares charges among the plurality of output terminals in response to a charge sharing control signal. The sharing voltage level control switch circuit controls charge sharing between the plurality of output terminals and a voltage level upon charge sharing, in response to a sharing voltage level control signal.