Patents by Inventor Hyun Jae Woo

Hyun Jae Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240116044
    Abstract: An atomic layer deposition method for manufacturing a platinum-based alloy catalyst includes applying a support in a reactor and depositing an alloy of platinum and a non-platinum metal on the support through a super cycle comprising a first sub-cycle and a second sub-cycle.
    Type: Application
    Filed: April 19, 2023
    Publication date: April 11, 2024
    Inventors: Jung Yeon Park, Woong Pyo Hong, Seung Jeong Oh, Se Hun Kwon, Susanta Bera, Hyun Jae Woo, Woo Jae Lee
  • Patent number: 9799092
    Abstract: A method and apparatus for processing graphic data, which are capable of decreasing a bandwidth of a memory, are provided. The method of processing graphic data includes receiving first graphic data and processing the first graphic data to generate second graphic data, and storing the generated second graphic data in a first shared memory line in which a state bit is set to a first state, wherein the first shared memory line is included in a first memory line set which is a part of an n-way set associative cache structure (n is a natural number equal to or greater than 2), at least one of the memory lines of the first memory line set is set to a second state which is different from the first state, and the state bit represents whether data stored in the memory line is replaceable.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: October 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Wan Bae, Hyun-Jae Woo
  • Patent number: 9665977
    Abstract: Provided is an apparatus and method for controlling rendering quality. The method for controlling rendering quality includes a thermal sensor sensing a temperature of a chip, a hull shader determining a level of detail (LOD) based on the temperature; and a tessellator tessellating segments that are divided according to the level of detail.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: May 30, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyun-Jae Woo
  • Publication number: 20160086303
    Abstract: A method and apparatus for processing graphic data, which are capable of decreasing a bandwidth of a memory, are provided. The method of processing graphic data includes receiving first graphic data and processing the first graphic data to generate second graphic data, and storing the generated second graphic data in a first shared memory line in which a state bit is set to a first state, wherein the first shared memory line is included in a first memory line set which is a part of an n-way set associative cache structure (n is a natural number equal to or greater than 2), at least one of the memory lines of the first memory line set is set to a second state which is different from the first state, and the state bit represents whether data stored in the memory line is replaceable.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 24, 2016
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Wan BAE, Hyun-Jae WOO
  • Publication number: 20160063760
    Abstract: Provided is an apparatus and method for controlling rendering quality. The method for controlling rendering quality includes a thermal sensor sensing a temperature of a chip, a hull shader determining a level of detail (LOD) based on the temperature; and a tessellator tessellating segments that are divided according to the level of detail.
    Type: Application
    Filed: March 25, 2015
    Publication date: March 3, 2016
    Inventor: Hyun-Jae Woo
  • Publication number: 20100045683
    Abstract: Techniques, apparatus and system are described for providing a hardware-type vector graphics acceleration. In one aspect, a hardware-type vector graphics accelerator includes graphics processing modules to communicate with a controller unit. The graphics processing modules include at least one of a rasterizing setup module, a scissor module, a paint generation module, an alpha masking module, and a blending module connected together according to a pipeline architecture to perform two-dimensional (2D) vector graphics acceleration in response to one or more commands received from the controller unit.
    Type: Application
    Filed: April 21, 2009
    Publication date: February 25, 2010
    Inventors: YOUNG OUK KIM, HYUN JAE WOO, CHAY HYUN KIM
  • Publication number: 20090231332
    Abstract: Techniques, apparatus and system for processing 3D graphics are provided. A graphics processor includes a fixed pipeline code generator to convert an application programming interface (API) supporting a fixed pipeline into first microcodes, a shader pipeline code generator to convert an API supporting a programmable pipeline into second microcodes, and a shader pipeline to process the first or second microcodes by using a shader program.
    Type: Application
    Filed: March 11, 2009
    Publication date: September 17, 2009
    Applicants: Core Logic, Inc., Korea Advanced Institute of Science and Technology
    Inventors: Hyun Jae Woo, Jeong Ae Park, Jeong Ho Woo