Patents by Inventor HYUN-JEONG ROH

HYUN-JEONG ROH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11189639
    Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: November 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-young Kim, Chang-beom Kim, Hyun-jeong Roh, Tae-joong Song, Dal-hee Lee, Sung-we Cho
  • Publication number: 20200235126
    Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.
    Type: Application
    Filed: April 8, 2020
    Publication date: July 23, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-young KIM, Chang-beom Kim, Hyun-jeong Roh, Tae-joong Song, Dal-hee Lee, Sung-we Cho
  • Patent number: 10691859
    Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Woo Seo, Ha-Young Kim, Hyun-Jeong Roh
  • Patent number: 10651201
    Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-young Kim, Chang-beom Kim, Hyun-jeong Roh, Tae-joong Song, Dal-hee Lee, Sung-we Cho
  • Publication number: 20180294280
    Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.
    Type: Application
    Filed: March 6, 2018
    Publication date: October 11, 2018
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-young KIM, Chang-beom KIM, Hyun-jeong ROH, Tae-joong SONG, Dal-hee LEE, Sung-we CHO
  • Publication number: 20180189438
    Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.
    Type: Application
    Filed: February 28, 2018
    Publication date: July 5, 2018
    Inventors: JAE-WOO SEO, HA-YOUNG KIM, HYUN-JEONG ROH
  • Patent number: 9934347
    Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: April 3, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Woo Seo, Ha-Young Kim, Hyun-Jeong Roh
  • Publication number: 20160098509
    Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.
    Type: Application
    Filed: September 29, 2015
    Publication date: April 7, 2016
    Inventors: JAE-WOO SEO, HA-YOUNG KIM, HYUN-JEONG ROH