Abstract: An overlay mark forming a Moire pattern, an overlay measurement method using the overlay mark, an overlay measurement apparatus using the overlay mark, and a manufacturing method of a semiconductor device using the overlay mark are provided. The overlay mark for measuring an overlay based on an image is configured to determine a relative misalignment between at least two pattern layers. The overlay mark includes a first overlay mark including a pair of first grating patterns which has a first pitch along a first direction and which is rotationally symmetrical by 180 degrees, and includes a second overlay mark including a pair of second grating patterns and a pair of third grating patterns. The second grating patterns partially overlap the first grating patterns and are rotationally symmetrical by 180 degrees, and the third grating patterns partially overlap the first grating patterns and are rotationally symmetrical by 180 degrees.

Abstract: A calibration apparatus is provided. The calibration apparatus includes: an acquisition unit for acquiring a captured image from a capturing device that captures a specified region in which a plurality of markers are indicated; and an analysis unit for finding the physical size of each pixel in the captured image through the analysis of physical movement data of at least one of the specified region and the capturing device and the captured image.

Abstract: An overlay mark, an overlay measurement method using the same, and a manufacturing method of a semiconductor device using the same are provided. The overlay mark is for measuring an overlay based on an image, is configured to determine a relative misalignment between at least two pattern layers, and includes first to fourth overlay marks. The first overlay mark has a pair of first Moire patterns disposed on a center portion of the overlay mark. The second overlay mark has a pair of second Moire patterns disposed so as to face each other with the first Moire patterns interposed therebetween. The third overlay mark has a pair of third Moire patterns disposed on a first diagonal line with the first Moire patterns interposed therebetween. The fourth overlay mark has a pair of fourth Moire patterns disposed on a second diagonal line with the first Moire patterns interposed therebetween.

Abstract: An overlay mark forming a Moire pattern, an overlay measurement method using the overlay mark, an overlay measurement apparatus using the overlay mark, and a manufacturing method of a semiconductor device using the overlay mark are provided. The overlay mark for measuring an overlay based on an image is configured to determine a relative misalignment between at least two pattern layers. The overlay mark includes a first overlay mark including a pair of first grating patterns which has a first pitch along a first direction and which is rotationally symmetrical by 180 degrees, and includes a second overlay mark including a pair of second grating patterns and a pair of third grating patterns. The second grating patterns partially overlap the first grating patterns and are rotationally symmetrical by 180 degrees, and the third grating patterns partially overlap the first grating patterns and are rotationally symmetrical by 180 degrees.

Abstract: An overlay mark, an overlay measurement method using the same, and a manufacturing method of a semiconductor device using the same are provided. The overlay mark is for measuring an overlay based on an image, is configured to determine a relative misalignment between at least two pattern layers, and includes first to fourth overlay marks. The first overlay mark has a pair of first Moire patterns disposed on a center portion of the overlay mark. The second overlay mark has a pair of second Moire patterns disposed so as to face each other with the first Moire patterns interposed therebetween. The third overlay mark has a pair of third Moire patterns disposed on a first diagonal line with the first Moire patterns interposed therebetween. The fourth overlay mark has a pair of fourth Moire patterns disposed on a second diagonal line with the first Moire patterns interposed therebetween.

Abstract: Provided are an overlay mark, and an overlay measurement method and a semiconductor device manufacturing method using the overlay mark. Specifically, provided is an overlay mark for determining relative misalignment between two or more pattern layers or between two or more patterns separately formed in one pattern layer, the overlay mark including a first overlay mark positioned in the center, a second overlay mark positioned above and below the first overlay mark or on the left and right thereof, and a third overlay mark and a fourth overlay mark each positioned in a diagonal line with the first overlay mark in between.

Abstract: Provided are an overlay mark, and an overlay measurement method and a semiconductor device manufacturing method using the overlay mark. Specifically, provided is an overlay mark for determining relative misalignment between two or more pattern layers or between two or more patterns separately formed in one pattern layer, the overlay mark including a first overlay mark positioned in the center, a second overlay mark positioned above and below the first overlay mark or on the left and right thereof, and a third overlay mark and a fourth overlay mark each positioned in a diagonal line with the first overlay mark in between.

Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.