Abstract: Apparatuses and methods for image processing are provided. The image processing apparatus performs area classification and object detection in an image, and includes a feature map generator configured to generate the feature map of the input image using the neural network, and an image processor configured to classify the areas and to detect the objects in the image using the generated feature map.

Abstract: Disclosed is an apparatus and method to train an autonomous driving model. The apparatus includes a driver information collection processor configured to collect driver information while a vehicle is being driven. The apparatus also includes a sensor information collection processor configured to collect sensor information from a sensor installed in the vehicle while the vehicle is being driven, and a model training processor configured to train the autonomous driving model based on the driver information and the sensor information.

Abstract: Disclosed are methods and apparatuses for object recognition using an artificial neural network. An object recognition apparatus includes an adjacent pixel setter configured to set the neighboring pixel pairs in the image frame, each neighboring pixel pair including first pixel and one or more second pixels adjacent to the first pixel, a labeler configured to label the first pixel using deep neural network-based model based on probability density function value of the neighboring pixel pairs, and an object recognizer configured to recognize an object based on the labeled first pixel.

Abstract: A method of operating a data storage device performing garbage collection in response to locality information for pages of a data block. The method includes acquiring mapping table information for the plurality of pages, and determining validity of each one of the plurality of pages while scanning mapping tables indicated by mapping table information associated with the plurality of pages.

Abstract: A storage device includes a flash memory and a memory controller. The flash memory includes a plurality of memory blocks. The memory controller is configured to determine a fast cycle weight corresponding to a reuse period of a selected memory block among the plurality of memory blocks, and to manage wear leveling of the selected memory block using the fast cycle weight.

Abstract: Disclosed is an address mapping method for a data storage device using a hybrid mapping scheme. The address mapping method determines whether write data includes a defined super sequential block (SSB), and selects an address mapping mode for the write data in accordance with whether or not a SSB is present.

Abstract: A data storage device includes a non-volatile memory device and a controller configured to receive a command from a host and to control an operation of the non-volatile memory device based on the command. The controller includes a processor configured to receive and process the command and an address extractor configured to extract address information from the command and to output the address information to the processor before the processor processes the command.

Abstract: A method of programming a storage device includes determining, at a controller of the storage device, that a first program mode of a plurality of program modes is to be entered in response to first information, wherein the first information includes a parameter associated with temperature, power consumption or input/output workload, and changing, using the controller, a program ratio of a first programming and a second programming of the storage device in the first program mode.

Abstract: An electrode assembly and a rechargeable battery that can prevent an active material from separating and prevent a short circuit and damage due to a tab that is attached to a current collector are provided. The electrode assembly includes a positive electrode, a negative electrode, and a separator that is disposed between the positive electrode and the negative electrode. The positive electrode has a positive electrode coating portion in which a positive electrode active material layer is formed and a positive electrode uncoated region in which a positive electrode active material layer is not formed, and a positive electrode tab is attached to the positive electrode uncoated region.

Abstract: A rechargeable battery that includes: an electrode assembly with a first electrode and a second electrode that include uncoated regions and coated regions; a case; a first electrode tab and a second electrode tab coupled to the first and second electrodes; and a laminating tape attached to opposite surfaces of a front end portion disposed at a center of the electrode assembly and opposite surfaces of a terminal end portion disposed at an outermost side of the electrode assembly.

Abstract: There is provided an oral appliance including: a body having a shape corresponding to a teeth arrangement; an upper teeth recess formed in an upper portion of the body to allow teeth included in the teeth arrangement of an upper jaw to be inserted therein; and a lower teeth recess formed in a lower portion of the body to allow teeth included in the teeth arrangement of a lower jaw to be inserted therein and allowing the lower jaw to move forward by a predetermined distance.

Abstract: There is provided an oral appliance including: a body having a shape corresponding to a teeth arrangement; an upper teeth recess formed in an upper portion of the body to allow teeth included in the teeth arrangement of an upper jaw to be inserted therein; and a lower teeth recess formed in a lower portion of the body to allow teeth included in the teeth arrangement of a lower jaw to be inserted therein and allowing the lower jaw to move forward by a predetermined distance.

Abstract: A data storing method of a nonvolatile storage device that includes a plurality of nonvolatile memory devices electrically connected to a plurality of channels is provided. The data storing method includes allocating part of write data provided from a host to the nonvolatile memory devices to each channel; determining whether at least one channel among the channels is present that is connected to a nonvolatile memory device in a last page offset state; and when the at least one channel is determined to be present, scheduling erase commands on the plurality of channels, scheduling write commands on the plurality of channels with respect to the allocated write data, and executing the erase commands and the write commands on the plurality of channels.

Abstract: A method and apparatus for improving application processing speed in a digital device which improve application processing speed for a digital device running in an embedded environment where processor performance may not be sufficiently powerful by detecting an execution request for an application, identifying a group to which the requested application belongs, among preset groups with different priorities and scheduling the requested application according to the priority assigned to the identified group, and executing the requested application based on the scheduling result.

Abstract: A method of manufacturing a ceramic filter for hot gas filtration, and, more particularly, to a method of manufacturing a ceramic filter for hot gas filtration through a drying process. The ceramic filter manufactured by the method is advantageous in that the pore size thereof can be easily adjusted, and the filtering area thereof can be maximized, thus improving the performance thereof. Consequently, the method of manufacturing a ceramic filter can be usefully used in the filter-related industry because a high-performance ceramic filter can be manufactured at a low cost and at low energy.

Abstract: Disclosed is a storage device which includes a flash memory storing data; and a controller controlling the flash memory and performing an invalidation operation in response to a trim command of a host, wherein the controller configures a trim sector bitmap using trim information provided from the host at the invalidation operation and manage the trim sector bitmap by a region unit.

Abstract: A signal detecting circuit of an infrared sensor includes: a cell array in which bolometers sensing infrared rays and outputting signal currents are arranged in an N×M format; a level generator that outputs a plurality of bias voltages corresponding to a plurality of bias levels; N resistor non-uniformity correcting circuits that are located in a column direction of the cell array and supply different bias voltages to each of the bolometers; M resistor non-uniformity correcting circuits that are located in a row direction of the cell array and supply different bias voltages to each of the bolometers; a control unit that sets a bias voltage level of each resistor non-uniformity correcting circuit to correct the resistor non-uniformity of the cell array; and N integrators that integrate the signal currents output from the cell array.

Abstract: A data storing method of a nonvolatile storage device that includes a plurality of nonvolatile memory devices electrically connected to a plurality of channels is provided. The data storing method includes allocating part of write data provided from a host to the nonvolatile memory devices to each channel; determining whether at least one channel among the channels is present that is connected to a nonvolatile memory device in a last page offset state; and when the at least one channel is determined to be present, scheduling erase commands on the plurality of channels, scheduling write commands on the plurality of channels with respect to the allocated write data, and executing the erase commands and the write commands on the plurality of channels.

Abstract: A signal detecting circuit of an infrared sensor includes: a cell array in which bolometers sensing infrared rays and outputting signal currents are arranged in an N×M format; a level generator that outputs a plurality of bias voltages corresponding to a plurality of bias levels; N resistor non-uniformity correcting circuits that are located in a column direction of the cell array and supply different bias voltages to each of the bolometers; M resistor non-uniformity correcting circuits that are located in a row direction of the cell array and supply different bias voltages to each of the bolometers; a control unit that sets a bias voltage level of each resistor non-uniformity correcting circuit to correct the resistor non-uniformity of the cell array; and N integrators that integrate the signal currents output from the cell array.