Abstract: Disclosed is an image sensor having A/D conversion circuitry coupled to column data lines of an image sensor array. The A/D conversion circuitry digitizes analog signals on the column data lines, each representing intensity of light incident upon an active imager cell. Higher resolution is provided for darker light levels than for bright light levels, such that a high resolution image is obtained with less storage data than would otherwise be required. In one embodiment, the A/D conversion circuitry includes a plurality of comparators, each having a first input coupled to one or more column data lines and a second input coupled to receive a time-varying reference signal, and a plurality of n-bit counters coupled to the comparator outputs. An n-bit to m-bit converter nonlinearly maps n-bit codes to m-bit codes and provides the m-bit codes to an m-bit D/A converter which produces the time-varying reference signal.

Abstract: Disclosed is an image sensing device having a reduced number of transistors within each imager cell as compared to prior art devices. Each imager cell includes a photosensitive element providing a photocharge responsive to incoming light, and first, second and third transistors. The first transistor is coupled to an activation line, e.g., a row select line, that carries an activation signal to a first plurality of imager cells to selectively activate cells for image data readout. This transistor transfers the photocharge towards a reference circuit node within the image cell in response to the activation signal. The second transistor is operably coupled to the first transistor, and is operative to selectively set a voltage level at the reference node. The third transistor has a control terminal coupled to the reference node, and an output terminal coupled to an output data bus common to a second plurality of image cells, e.g., a column of cells.

Abstract: Disclosed is a circuit for performing correlated double sampling entirely in the digital domain. In an exemplary embodiment, the circuit includes a plurality of comparators, each having a first input coupled to an associated data line for receiving first and second signals in first and second sampling intervals, respectively. A time varying reference signal is applied to the second input of each comparator. A plurality of up/down counters are coupled to respective ones of the comparators, and each is operable to count in a first direction during the first sampling interval and in an opposite direction during the second sampling interval. Each up/down counter is caused to stop counting when the amplitude of the variable reference signal substantially equals the amplitude of the respective first or second signal. As a result, each up/down counter provides an output representing a subtraction of one of said first or second signals from the other.

Abstract: An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current. In one embodiment, the apparatus comprises a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output. The body is adapted for connection to the charge pump output. The apparatus further comprises a control circuit having an input adapted for connection to the charge pump output and an output connected to the bleeder circuit input. The control circuit provides a voltage potential to the input of the current bleeder circuit to control the gate-to-source voltage of the current bleeder circuit transistor.

Abstract: A discharge circuit for a semiconductor memory includes a first node, a second node for receiving a control signal having first and second states, and a circuit connected between the first node and ground potential and to the second node. The circuit couples the first node to ground potential when the control signal has the first state and substantially isolates the first node from ground potential when the control signal has the second state. The circuit includes a first subcircuit for defining a current path between the first node and ground potential. The first subcircuit includes a plurality of transistors connected in series, each of which having a gate, source and drain. The circuit further includes a second subcircuit for effecting predetermined gate-to-source, and drain-to-source voltages of the transistors of the first subcircuit when the control signal has the second state.

Abstract: High performance on-chip voltage regulator designs are disclosed which have settling times which are fast enough to meet today's microprocessor/microcontroller requirements when they are entering an active mode from a passive mode. A first preferred embodiment provides a circuit in which a single pulse control signal is required to instantly raise Vy when the microprocessor is in the wake-up period. The circuit includes a charge pump, a differential amplifier, and a microprocessor connected to the power supply through a voltage regulating device. A second embodiment provides a circuit to stimulate Vint prior to CPU wake-up. The principle of operation of this embodiment is to stimulate the voltage regulating device prior to CPU wake-up. By stimulating (pulling down) the Vint node, the voltage regulating device will raise Vy and ready the microprocessor to draw a large current.

Abstract: A self-biased, fully differential, complementary receiver apparatus and method is presented. The receiver accepts differential inputs that can vary over the full rail-to-rail common mode voltage range. It produces double-ended complementary outputs swinging rail-to-rail useful in signal level conversion and comparator applications. The receiver includes a dual, fully complementary and mirror-symmetrical arrangement of a differential input stage, a biasing stage and an output stage. A self biasing voltage is generated with a balanced voltage divider coupled between the outputs of the biasing stages. This frees both biasing outputs for use as analogous but complementary receiver outputs while providing the receiver with all the advantages of self bias. For small signal differential inputs, the input and biasing stages operate in their linear region useful for amplifier applications.