Patents by Inventor Hyun-Joo Cha

Hyun-Joo Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9276058
    Abstract: A semiconductor device includes a plurality of lower electrodes on a substrate, with each of the lower electrodes extending in a height direction from the substrate and including sidewalls, the lower electrodes being spaced apart from each other in a first direction and in a second direction, a plurality of first supporting layer patterns contacting the sidewalls of the lower electrodes, the first supporting layer patterns extending in the first direction between ones of the lower electrodes adjacent in the second direction, a plurality of second supporting layer patterns contacting the sidewalls of the lower electrodes, the second supporting layer pattern extending in the second direction between ones of the lower electrodes adjacent in the first direction, the plurality of second supporting layer patterns being spaced apart from the plurality of first supporting layer patterns in the height direction.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: March 1, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Ho Lee, Jin Choi, Yong-Ho Yoo, Jong-Hyuk Kang, Hyun-Joo Cha, Hee-Dong Park, Tae-Jung Park
  • Publication number: 20150270330
    Abstract: A semiconductor device includes a plurality of lower electrodes on a substrate, with each of the lower electrodes extending in a height direction from the substrate and including sidewalls, the lower electrodes being spaced apart from each other in a first direction and in a second direction, a plurality of first supporting layer patterns contacting the sidewalls of the lower electrodes, the first supporting layer patterns extending in the first direction between ones of the lower electrodes adjacent in the second direction, a plurality of second supporting layer patterns contacting the sidewalls of the lower electrodes, the second supporting layer pattern extending in the second direction between ones of the lower electrodes adjacent in the first direction, the plurality of second supporting layer patterns being spaced apart from the plurality of first supporting layer patterns in the height direction.
    Type: Application
    Filed: June 5, 2015
    Publication date: September 24, 2015
    Inventors: Sung-Ho LEE, Jin CHOI, Yong-Ho YOO, Jong-Hyuk KANG, Hyun-Joo CHA, Hee-Dong PARK, Tae-Jung PARK
  • Patent number: 9054226
    Abstract: A semiconductor device includes a plurality of lower electrodes on a substrate, with each of the lower electrodes extending in a height direction from the substrate and including sidewalls, the lower electrodes being spaced apart from each other in a first direction and in a second direction, a plurality of first supporting layer patterns contacting the sidewalls of the lower electrodes, the first supporting layer patterns extending in the first direction between ones of the lower electrodes adjacent in the second direction, a plurality of second supporting layer patterns contacting the sidewalls of the lower electrodes, the second supporting layer pattern extending in the second direction between ones of the lower electrodes adjacent in the first direction, the plurality of second supporting layer patterns being spaced apart from the plurality of first supporting layer patterns in the height direction.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: June 9, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Ho Lee, Jin Choi, Yong-Ho Yoo, Jong-Hyuk Kang, Hyun-Joo Cha, Hee-Dong Park, Tae-Jung Park
  • Publication number: 20130015559
    Abstract: A semiconductor device includes a plurality of lower electrodes on a substrate, with each of the lower electrodes extending in a height direction from the substrate and including sidewalls, the lower electrodes being spaced apart from each other in a first direction and in a second direction, a plurality of first supporting layer patterns contacting the sidewalls of the lower electrodes, the first supporting layer patterns extending in the first direction between ones of the lower electrodes adjacent in the second direction, a plurality of second supporting layer patterns contacting the sidewalls of the lower electrodes, the second supporting layer pattern extending in the second direction between ones of the lower electrodes adjacent in the first direction, the plurality of second supporting layer patterns being spaced apart from the plurality of first supporting layer patterns in the height direction.
    Type: Application
    Filed: July 11, 2012
    Publication date: January 17, 2013
    Inventors: Sung-Ho LEE, Jin Choi, Yong-Ho Yoo, Jong-Hyuk Kang, Hyun-Joo Cha, Hee-Dong Park, Tae-Jung Park
  • Publication number: 20120049257
    Abstract: A DRAM device can include a plurality of capacitors that are arranged in a line in a first direction. Each of the capacitors can include an upper electrode. A contact pattern having a line shape can extend in the first direction and can be electrically connected to each of the upper electrodes. A conductor can be on the contact pattern opposite the upper electrodes and can be electrically connected to the contact pattern.
    Type: Application
    Filed: August 12, 2011
    Publication date: March 1, 2012
    Inventors: SungHo Lee, Jin Choi, Yong-Ho Yoo, Jong-Hyuk Kang, Hyun-Joo Cha, Tae-Jung Park