Abstract: A catalyst for preparing carbon nanotubes where a catalyst component is supported on a support coated with carbon, and a method for preparing the catalyst is described.

Abstract: The present invention relates to a method for preparing carbon nanotubes, the method including: preparing a support including AlO(OH) by primary heat treatment of Al(OH)3; preparing an active carrier by supporting a mixture including a main catalyst precursor and a cocatalyst precursor on the support; drying the active carrier through multi-stage drying including vacuum drying; preparing a supported catalyst by secondary heat treatment of the dried active support; and preparing carbon nanotubes in the presence of the supported catalyst, and the carbon nanotubes prepared by the method as described above can remarkably improve conductivity.

Abstract: The present invention relates to a supported catalyst for producing carbon nanotubes which includes a carrier having a number average particle size (DMN) of 1.5 ?m to 20 ?m, and an active ingredient supported in the carrier, wherein the active ingredient which prevents the aggregation between particles and supports the particles may act as an active ingredient, so that it is possible to provide a supported catalyst which has excellent activity, and thus, which may improve the production yield.

Abstract: The present invention relates to carbon nanotubes having a pore volume of 0.94 cm3/g or more, and being an entangled type, a method of manufacturing the same, and a positive electrode for a primary battery which comprises the same.

Abstract: The present invention relates to a method for preparing a carbon nanotube dispersion, the method including mixing a dispersion solution including a dispersion solvent and a dispersant with carbon nanotubes to prepare carbon nanotube paste, extruding the paste to obtain solid carbon nanotubes, and introducing a second solvent to the solid carbon nanotubes, and homogenizing the carbon nanotubes, wherein the weight ratio of the dispersion solution and the carbon nanotubes is 1:1 to 9:1. According to the present invention, the mixing of a dispersant and carbon nanotubes is increased and the particle size is controlled by a wet method, so that a carbon nanotube dispersion having a viscosity controlled to a low level, excellent resistance properties, and a high concentration, may be provided.

Abstract: The present invention relates to a bundle-type carbon nanotube which has a bulk density of 25 to 45 kg/m3, a ratio of the bulk density to a production yield of 1 to 3, and a ratio of a tap density to the bulk density of 1.3 to 2.0, and a method for preparing the same.

Abstract: The present invention relates to a bundle-type carbon nanotube which has a bulk density of 25 to 45 kg/m3, a ratio of the bulk density to a production yield of 1 to 3, and a ratio of a tap density to the bulk density of 1.3 to 2.0, and a method for preparing the same.

Abstract: A memory controller, an application processor, and a method of operating the memory controller can control performance and power consumption of an input/output device. The method includes allowing the memory device to enter a power down mode after an idle state is maintained for a first time period corresponding to a first setting value which is currently set, allowing the memory device to enter from the power down mode into an active state when access to the memory device occurs, determining a maintenance time of the power down mode to change the first setting value to a second setting value, based on a result obtained by monitoring a driving pattern of the memory device, and when the idle state is maintained for a second time period different from the first time period, allowing the memory device to enter the power down mode, based on the second setting value.

Abstract: The present invention relates to carbon nanotubes having a pore volume of 0.94 cm3/g or more, and being an entangled type, a method of manufacturing the same, and a positive electrode for a primary battery which comprises the same.

Abstract: Provided are a memory controller and an application processor (AP) for controlling utilization and performance of an input/output (I/O) device and a method of operating the memory controller. The memory controller includes an address translator configured to translate a first address received from a host processor into a second address indicating a memory address based on an address translation scheme selected from a plurality of address translation schemes based on memory resource utilization; and an evaluation module configured to evaluate the memory resource utilization of each of the plurality of address translation schemes based on a plurality of memory addresses generated based on each of the plurality of address translation schemes.

Abstract: The present invention relates to a method for preparing a carbon nanotube dispersion, the method including mixing a dispersion solution including a dispersion solvent and a dispersant with carbon nanotubes to prepare carbon nanotube paste, extruding the paste to obtain solid carbon nanotubes, and introducing a second solvent to the solid carbon nanotubes, and homogenizing the carbon nanotubes, wherein the weight ratio of the dispersion solution and the carbon nanotubes is 1:1 to 9:1. According to the present invention, the mixing of a dispersant and carbon nanotubes is increased and the particle size is controlled by a wet method, so that a carbon nanotube dispersion having a viscosity controlled to a low level, excellent resistance properties, and a high concentration, may be provided.

Abstract: The present invention relates to a bundle-type carbon nanotube which has a bulk density of 25 to 45 kg/m3, a ratio of the bulk density to a production yield of 1 to 3, and a ratio of a tap density to the bulk density of 1.3 to 2.0, and a method for preparing the same.

Abstract: Provided are a memory controller and an application processor (AP) for controlling utilization and performance of an input/output (I/O) device and a method of operating the memory controller. The memory controller includes an address translator configured to translate a first address received from a host processor into a second address indicating a memory address based on an address translation scheme selected from a plurality of address translation schemes based on memory resource utilization; and an evaluation module configured to evaluate the memory resource utilization of each of the plurality of address translation schemes based on a plurality of memory addresses generated based on each of the plurality of address translation schemes.

Abstract: A memory controller, an application processor, and a method of operating the memory controller can control performance and power consumption of an input/output device. The method includes allowing the memory device to enter a power down mode after an idle state is maintained for a first time period corresponding to a first setting value which is currently set, allowing the memory device to enter from the power down mode into an active state when access to the memory device occurs, determining a maintenance time of the power down mode to change the first setting value to a second setting value, based on a result obtained by monitoring a driving pattern of the memory device, and when the idle state is maintained for a second time period different from the first time period, allowing the memory device to enter the power down mode, based on the second setting value.

Abstract: Provided is a method of driving a system-on-chip (SOC). The method includes adding a first transaction to a list, allocating the first transaction to a first slot, determining whether a second transaction is redundant, and adding the second transaction to the list and allocating the second transaction to the first slot when it is determined that the second transaction is redundant. Accordingly, the SOC can increase outstanding capability and enhance performance of a system interconnection.

Abstract: A write leveling control method which includes registering data-related signal (DRS) reference delay values corresponding to types of memory modules in a leveling reference table; transmitting write leveling-related signals to a first type of memory module mounted on a target board; detecting timing skews between a clock signal and data-related signals received from memory devices on the mounted memory module; and adjusting a delay of a data-related signal transmitted to a memory device of the mounted memory module if a corresponding timing skew is outside of a first range, based on the DRS reference delay value corresponding to the mounted memory module.

Abstract: A write leveling control method which includes registering data-related signal (DRS) reference delay values corresponding to types of memory modules in a leveling reference table; transmitting write leveling-related signals to a first type of memory module mounted on a target board; detecting timing skews between a clock signal and data-related signals received from memory devices on the mounted memory module; and adjusting a delay of a data-related signal transmitted to a memory device of the mounted memory module if a corresponding timing skew is outside of a first range, based on the DRS reference delay value corresponding to the mounted memory module.

Abstract: Provided is a method of driving a system-on-chip (SOC). The method includes adding a first transaction to a list, allocating the first transaction to a first slot, determining whether a second transaction is redundant, and adding the second transaction to the list and allocating the second transaction to the first slot when it is determined that the second transaction is redundant. Accordingly, the SOC can increase outstanding capability and enhance performance of a system interconnection.

Abstract: A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results.

Abstract: A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response to the request, and an interconnector configured to include a slave interface for providing the request to one or more master interfaces and for supplying response data to the first master device based on operation characteristics of the first master. An arbitration method of an interconnector transferring a plurality of response data provided from a plurality of slave devices to a master device comprises selecting one of a plurality of arbitration modes based on operation characteristics of the master device; and transferring the response data in the order determined by transfer priority corresponding to the selected arbitration mode.