Patents by Inventor Hyun Joung Kim

Hyun Joung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240117211
    Abstract: A paint composition is prepared by mixing each of an acrylic resin, an acrylic polyol resin, a polycarbonate diol resin, a diisocyanate, a solvent, and an antibacterial agent in appropriate amounts. As a result, the paint composition has improved physical properties and effective antibacterial activities.
    Type: Application
    Filed: April 28, 2023
    Publication date: April 11, 2024
    Inventors: Hyun Jung Kim, Ho Tak Jeon, Jae Sik Seo, Ji Hwan Park, Dae Joung Cho
  • Patent number: 8659175
    Abstract: An integrated circuit package system is provided including mounting a first integrated circuit device over a carrier, mounting a second integrated circuit device having an adhesive spacer over the first integrated circuit device in an offset configuration, connecting a first internal interconnect between the carrier and the first integrated circuit device with the first internal interconnect within the adhesive spacer, connecting a second internal interconnect between the carrier and the second integrated circuit device, and encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect and the second internal interconnect.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: February 25, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Jong Wook Ju, Taeg Ki Lim, Hyun Joung Kim
  • Patent number: 8217501
    Abstract: A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts; attaching an integrated circuit to the top surface; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that are over and larger than the electrical contacts.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: July 10, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Hyeog Chan Kwon, Hyun Joung Kim, Jae Chang Kim, Taeg Ki Lim, Jong Wook Ju
  • Patent number: 8059065
    Abstract: A method and apparatus for driving an electro-luminescence display panel capable of preventing an initial blinking phenomenon occurring at a power application is disclosed. In the method, a first electrode of the EL cell and a ground voltage source are opened during a first period from a turn-on time of a power source to shut off a current path of the EL cells. Then, the first electrode of the pixel matrix and the ground voltage source is shorted during a second period to form a current path such that the EL cells are light-emitted in accordance with a data supplied to the pixel matrix.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: November 15, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Hyun Joung Kim, Guen Bae Park, Won Kyu Ha
  • Patent number: 7978157
    Abstract: An electro-luminescence display device including red, green and blue reference gamma generators each having three digital analog converters or more in order to generate a reference gamma voltage of low gray level and a reference gamma voltage of high gray level, and at least one integrated circuit to generate a data signal in use of the reference gamma voltage of low gray level and the reference gamma voltage of high gray level. Each reference gamma generator includes a first digital analog converter to divide a voltage supplied to itself in order to generate i numbers of voltage levels, a second digital analog converter to divide a voltage supplied to itself in order to generate j numbers of voltage levels, and a third digital analog converter to receive two voltage levels from the second digital analog converter and to divides the two received voltage levels into j numbers of voltage levels.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: July 12, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Jung Min Seo, Hyun Joung Kim, Won Kyu Ha, Hak Su Kim, Guen Bae Park, Eun Myung Park, Kee Mog Shin
  • Publication number: 20100237488
    Abstract: A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts; attaching an integrated circuit to the top surface; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that are over and larger than the electrical contacts.
    Type: Application
    Filed: May 28, 2010
    Publication date: September 23, 2010
    Inventors: Hyeog Chan Kwon, Hyun Joung Kim, Jae Chang Kim, Taeg Ki Lim, Jong Wook Ju
  • Patent number: 7737539
    Abstract: An integrated circuit package system including a substrate with a top surface and a bottom surface. Configuring the top surface to include electrical contacts formed between a perimeter of the substrate and a semiconductor die. Aligning over the top surface of the substrate a mold plate with a honeycomb meshwork of posts or a stepped honeycomb meshwork of posts and depositing a material to prevent warpage of the substrate between the top surface of the substrate and the mold plate. Removing the mold plate to reveal discrete hollow conduits formed within the material that align with the electrical contacts.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: June 15, 2010
    Assignee: STATS Chippac Ltd.
    Inventors: Hyeog Chan Kwon, Hyun Joung Kim, Jae Chang Kim, Taeg Ki Lim, Jong Wook Ju
  • Patent number: 7687920
    Abstract: An integrated circuit package-on-package system includes: providing a base substrate having a central opening; attaching a bottom die below the base substrate partially covering the central opening, the bottom die connected through the central opening to a top surface of the base substrate; attaching a top die above the base substrate partially covering the central opening; attaching external conductive interconnections to a base bottom surface of the base substrate; and molding an encapsulant leaving the external conductive interconnections partially exposed.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: March 30, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: DeokKyung Yang, Jae Han Chung, Hyun Joung Kim
  • Patent number: 7663589
    Abstract: There is disclosed an electro-luminescence display device that is adaptive for preventing picture quality deterioration by operating a thin film transistor for an electro-luminescence cell drive at a non-saturation area to compensate a threshold voltage, and a driving method thereof.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: February 16, 2010
    Assignee: LG Electronics Inc.
    Inventors: Won Kyu Ha, Hak Su Kim, Jae Do Lee, Ki Heon Kim, Jung Min Seo, Hyun Joung Kim
  • Patent number: 7656017
    Abstract: An integrated circuit package system includes providing a plurality of substrates; inserting a receptor in one of the substrates, the receptor held in and not extending through the one of the substrates; inserting a conductive post in another of the substrates; mounting the one of the substrates and the another of the substrates over one another with the conductive post engaging the receptor to thermally interlock without a separate bonding material; and mounting an integrated circuit mounted on the one of the substrates or the another of the substrates.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: February 2, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Hyun Joung Kim, Taeg Ki Lim, Ja Eun Yun
  • Patent number: 7646365
    Abstract: A method and apparatus for driving an electro-luminescence display device capable of preventing a defect of signal lines caused by a relatively high scan voltage and current is disclosed. In the apparatus, a display panel has a scan line, a data line intersecting the scan line and supplied with a data, and a light-emitting device positioned at the intersection between the scan line and the data line. A data driver supplies a data to the data line. A scan driver applies a scanning pulse having a different current component to the scan line during a desired period.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: January 12, 2010
    Assignee: LG Electronics Inc.
    Inventors: Hyun Joung Kim, Hak Su Kim
  • Publication number: 20090256267
    Abstract: An integrated circuit package-on-package system includes: providing a base substrate having a central opening; attaching a bottom die below the base substrate partially covering the central opening, the bottom die connected through the central opening to a top surface of the base substrate; attaching a top die above the base substrate partially covering the central opening; attaching external conductive interconnections to a base bottom surface of the base substrate; and molding an encapsulant leaving the external conductive interconnections partially exposed.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 15, 2009
    Inventors: DeokKyung Yang, Jae Han Chung, Hyun Joung Kim
  • Publication number: 20090167650
    Abstract: An electro-luminescence display device including red, green and blue reference gamma generators each having three digital analog converters or more in order to generate a reference gamma voltage of low gray level and a reference gamma voltage of high gray level, and at least one integrated circuit to generate a data signal in use of the reference gamma voltage of low gray level and the reference gamma voltage of high gray level. Each reference gamma generator includes a first digital analog converter to divide a voltage supplied to itself in order to generate i numbers of voltage levels, a second digital analog converter to divide a voltage supplied to itself in order to generate j numbers of voltage levels, and a third digital analog converter to receive two voltage levels from the second digital analog converter and to divides the two received voltage levels into j numbers of voltage levels.
    Type: Application
    Filed: March 5, 2009
    Publication date: July 2, 2009
    Inventors: Jung Min Seo, Hyun Joung Kim, Won Kyu Ha, Hak Su Kim, Guen Bae Park, Eun Myung Park, Kee Mog Shin
  • Patent number: 7511688
    Abstract: The present invention relates to an electro-luminescence display that is adaptive for reducing its manufacturing cost as well as reducing its process time. An electro-luminescence display device according to an embodiment of the present invention includes a gamma generator to output a reference gamma voltage corresponding to a control data supplied from the outside; and at least one data integrated circuit to receive a data from the outside and to generate a data signal corresponding to the bit number of the data in use of the reference gamma voltage.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: March 31, 2009
    Assignee: LG Display Co., Ltd.
    Inventors: Jung Min Seo, Hyun Joung Kim, Won Kyu Ha, Hak Su Kim, Guen Bae Park, Eun Myung Park, Kee Mog Shin
  • Patent number: 7443037
    Abstract: A stacked integrated circuit package system is provided connecting an interconnect between a first integrated circuit device and a substrate, the first integrated circuit device on the substrate, applying a protective dot on the first integrated circuit device, mounting a second integrated circuit device, having an adhesive, on the protective dot, with the adhesive on the first integrated circuit device, connecting the second integrated circuit device and the substrate, and encapsulating the first integrated circuit device, the second integrated circuit device, and the interconnect.
    Type: Grant
    Filed: April 1, 2006
    Date of Patent: October 28, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Hyun Joung Kim, Jong Wook Ju, Taeg Ki Lim
  • Publication number: 20080142943
    Abstract: An integrated circuit package system includes providing a plurality of substrates; inserting a receptor in one of the substrates, the receptor held in and not extending through the one of the substrates; inserting a conductive post in another of the substrates; mounting the one of the substrates and the another of the substrates over one another with the conductive post engaging the receptor to thermally interlock without a separate bonding material; and mounting an integrated circuit mounted on the one of the substrates or the another of the substrates.
    Type: Application
    Filed: December 10, 2007
    Publication date: June 19, 2008
    Inventors: Hyun Joung Kim, Taeg Ki Lim, Ja Eun Yun
  • Publication number: 20070296086
    Abstract: An integrated circuit package system is provided including mounting a first integrated circuit device over a carrier, mounting a second integrated circuit device having an adhesive spacer over the first integrated circuit device in an offset configuration, connecting a first internal interconnect between the carrier and the first integrated circuit device with the first internal interconnect within the adhesive spacer, connecting a second internal interconnect between the carrier and the second integrated circuit device, and encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect and the second internal interconnect.
    Type: Application
    Filed: June 12, 2007
    Publication date: December 27, 2007
    Inventors: Jong Wook Ju, Taeg Ki Lim, Hyun Joung Kim
  • Publication number: 20070229107
    Abstract: A stacked integrated circuit package system is provided connecting an interconnect between a first integrated circuit device and a substrate, the first integrated circuit device on the substrate, applying a protective dot on the first integrated circuit device, mounting a second integrated circuit device, having an adhesive, on the protective dot, with the adhesive on the first integrated circuit device, connecting the second integrated circuit device and the substrate, and encapsulating the first integrated circuit device, the second integrated circuit device, and the interconnect.
    Type: Application
    Filed: April 1, 2006
    Publication date: October 4, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Hyun Joung Kim, Jong Wook Ju, Taeg Ki Lim
  • Publication number: 20070158806
    Abstract: An integrated circuit package system including a substrate with a top surface and a bottom surface. Configuring the top surface to include electrical contacts formed between a perimeter of the substrate and a semiconductor die. Aligning over the top surface of the substrate a mold plate with a honeycomb meshwork of posts or a stepped honeycomb meshwork of posts and depositing a material to prevent warpage of the substrate between the top surface of the substrate and the mold plate. Removing the mold plate to reveal discrete hollow conduits formed within the material that align with the electrical contacts.
    Type: Application
    Filed: January 12, 2006
    Publication date: July 12, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Hyeog Chan Kwon, Hyun Joung Kim, Jae Chang Kim, Taeg Ki Lim, Jong Wook Ju