Abstract: The present disclosure relates to a composition for a polymer electrolyte, a polymer electrolyte comprising the same, and a method for producing the polymer electrolyte, and specifically, to a composition for a polymer electrolyte comprising an ion conductive monomer and a polymerizable comonomer, and a polymer electrolyte comprising the same.

Abstract: A composition suitable for diagnosing a musculoskeletal disease and a composition suitable for preventing or treating a musculoskeletal disease are disclosed. The composition contains zinc finger protein with KRAB and SCAN domains 8 (Zkscan8) protein, which can be effectively used as an excellent biomarker for obtaining accurate information about the occurrence and progression stages of a musculoskeletal disease, specifically a tendon disease or a ligament disease. The compositions containing Zkscan8 can be effectively used for preventing or treating a musculoskeletal disease through Zkscan8 overexpression.

Abstract: The present disclosure relates to a composition for a polymer electrolyte, a polymer electrolyte comprising the same, and a method for producing the polymer electrolyte, and specifically, to a composition for a polymer electrolyte comprising an ion conductive monomer and a polymerizable comonomer, and a polymer electrolyte comprising the same.

Abstract: Provided herein are di-functionalized hyaluronic acids, such as molecules including (or that have been functionalized at) a thiol and azide side chain. Also, provided herein are hydrogels of these di-functionalized hyaluronic acids and methods of using these compounds to promote cell (e.g., neuronal cell) growth and development. In some aspects, the present disclosure also provides methods of treating injuries, including brain injuries such as stroke through the use of hydrogels of the compounds described herein and stem cells.

Abstract: A method of fabricating a semiconductor device including at least one of the following steps: forming an oxide layer on and/or over a silicon substrate. Forming a first photoresist pattern on and/or over the oxide layer. Forming a trench by etching the oxide layer and the substrate using the first photoresist pattern as a mask. Removing the first photoresist pattern. Filling the trench with a trench oxide layer. Planarizing the trench oxide layer. Forming an etch stop layer on and/or over the trench oxide layer. Forming a second photoresist pattern on and/or over the etch stop layer. Etching the etch stop layer and the trench oxide layer using the second photoresist pattern as an etch mask. Removing the second photoresist pattern and the etch stop layer.

Abstract: A flash device and a manufacturing method thereof are provided. An ONO pattern can be formed on a floating gate, and a control gate can be formed on the ONO pattern. The ONO pattern can be formed with a portion that projects farther out than the sides of the floating gate and the control gate.

Abstract: A method of manufacturing a flash memory device that prevents generation of voids when forming an interlayer dielectric film. The method may include forming a gate on a semiconductor substrate, and then sequentially stacking a first dielectric film and a second dielectric film on the semiconductor substrate, and then forming a first spacer comprising a first dielectric film pattern and a second dielectric film pattern on sidewalls of the gate by performing a first etching process, and then forming source and drain areas in the semiconductor substrate, and then removing the second dielectric film, and then sequentially stacking a third dielectric film and a fourth dielectric film on the semiconductor substrate, and then forming a second spacer comprising the first dielectric pattern and a third dielectric pattern on the sidewalls of the gate by performing a second etching process, and then forming an interlayer dielectric film on the semiconductor substrate including the gate and the first spacer.

Abstract: A method of manufacturing a semiconductor device begins when a first dielectric pattern is formed on and/or over a substrate, and a first etching process is performed to form a trench in the substrate. An edge portion of the first trench is exposed. An oxidation process is performed on and/or over the substrate rounding the edge portion of the trench. A second dielectric is formed on and/or over the substrate including the trench, and a planarization process is performed on the second dielectric. A photoresist pattern is formed on and/or over the second dielectric corresponding to the trench, and a second etching process is performed to form a second dielectric pattern filling the trench. The photoresist pattern is removed. A second cleaning process is performed on the substrate including the trench to form a device isolation layer, which is formed by removing a portion of the second dielectric pattern.

Abstract: Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, a transistor structure may be manufactured on a semiconductor substrate, and an insulating layer covering the transistor structure may be formed. The insulating layer may be patterned to form a first via that may expose the semiconductor substrate, and a silicon layer may be formed on the first via and the insulating layer. The silicon layer and the insulating layer may be patterned to form a second via exposing the transistor structure, and the second via may be filled with metal to form a connecting line electrically connected with the transistor structure. Conductive impurities may be implanted into the silicon layer and may form a light receiving portion connected with the connecting line.

Abstract: A method of fabricating a semiconductor device is provided. Spacers can be formed on adjacent gate structures and used as an ion implantation mask for forming source/drain regions. The spacers can include a nitride layer and an oxide layer. An etch stop layer can be provided between the gate structures, and the oxide layer can be removed from the spacers. A first oxide layer formed below the nitride layer can be protected from being etched away during removal of the oxide layer from the spacers by the etch stop layer. The etch stop layer and the first oxide layer can be removed, and an interlayer dielectric layer can be deposited.

Abstract: A method of forming a dual damascene pattern for a metal interconnection by a relatively simple process. Only a portion of an interlayer insulating film is initially etched when forming a via hole. When the interlayer insulating is etched to form a trench, the remaining portion of the via hole may be etched simultaneously.

Abstract: A thieno[3,2-b]indole-based polymer and an organo-electroluminescent device in which the polymer is introduced into an organic layer are provided. The thieno[3,2-b]indole-based polymer may be easily prepared and has blue light-emitting characteristic. The organo-electroluminescent device adopting the organic layer using the thieno[3,2-b]indole-based polymer has improved color purity, efficiency, and luminance characteristics.

Abstract: A method of manufacturing a flash memory device that prevents generation of voids when forming an interlayer dielectric film. The method may include forming a gate on a semiconductor substrate, and then sequentially stacking a first dielectric film and a second dielectric film on the semiconductor substrate, and then forming a first spacer comprising a first dielectric film pattern and a second dielectric film pattern on sidewalls of the gate by performing a first etching process, and then forming source and drain areas in the semiconductor substrate, and then removing the second dielectric film, and then sequentially stacking a third dielectric film and a fourth dielectric film on the semiconductor substrate, and then forming a second spacer comprising the first dielectric pattern and a third dielectric pattern on the sidewalls of the gate by performing a second etching process, and then forming an interlayer dielectric film on the semiconductor substrate including the gate and the first spacer.

Abstract: Disclosed is a flash memory device. The flash memory device includes a plurality of trench lines in an isolation region of a semiconductor device, a common source region along a word line (WL) direction under a surface portion of the semiconductor substrate, a plurality of gate lines along a vertical direction of the trench line, a drain region on an opposite side of the gate line to the common source region, a drain contact over the drain region, and a uniform by-product layer on the common source region.

Abstract: A method of manufacturing a semiconductor device begins when a first dielectric pattern is formed on and/or over a substrate, and a first etching process is performed to form a trench in the substrate. An edge portion of the first trench is exposed. An oxidation process is performed on and/or over the substrate rounding the edge portion of the trench. A second dielectric is formed on and/or over the substrate including the trench, and a planarization process is performed on the second dielectric. A photoresist pattern is formed on and/or over the second dielectric corresponding to the trench, and a second etching process is performed to form a second dielectric pattern filling the trench. The photoresist pattern is removed. A second cleaning process is performed on the substrate including the trench to form a device isolation layer, which is formed by removing a portion of the second dielectric pattern.

Abstract: Disclosed is a flash memory device. The flash memory device includes a plurality of trench lines in an isolation region of a semiconductor device, a common source region along a word line (WL) direction under a surface portion of the semiconductor substrate, a plurality of gate lines along a vertical direction of the trench line, a drain region on an opposite side of the gate line to the common source region, a drain contact over the drain region, and a uniform by-product layer on the common source region.

Abstract: An image sensor and a method for manufacturing the same are provided. The image sensor can include: a semiconductor substrate including a circuit area; a metal interconnection layer including a metal interconnection and a an interlayer dielectric layer on the semiconductor substrate; a first conductive-type pattern on the metal interconnection layer; an intrinsic layer pattern having a dome-like shape on the first conductive-type pattern; and a second conductive-type conductive layer on the metal interconnection layer including the intrinsic layer pattern.

Abstract: A flash device and a manufacturing method thereof are provided. An ONO pattern can be formed on a floating gate, and a control gate can be formed on the ONO pattern. The ONO pattern can be formed with a portion that projects farther out than the sides of the floating gate and the control gate.

Abstract: A method for manufacturing a semiconductor device is provided. A first gate can be formed in a salicide region of a semiconductor substrate, and a second gate can be formed in a non-salicide region of the semiconductor substrate. A source and a drain can be formed at both sides of each of the first and second gates. An insulating layer covering the first and second gates can be formed, and first and second spacers can be formed on the insulating layer. The non-salicide region can be covered with a mask, and the insulating layer of the salicide region can be selectively removed. Salicide can then be formed on the first gate, and the source and drain of the first gate.

Abstract: A method of fabricating a semiconductor device is provided. Spacers can be formed on adjacent gate structures and used as an ion implantation mask for forming source/drain regions. The spacers can include a nitride layer and an oxide layer. An etch stop layer can be provided between the gate structures, and the oxide layer can be removed from the spacers. A first oxide layer formed below the nitride layer can be protected from being etched away during removal of the oxide layer from the spacers by the etch stop layer. The etch stop layer and the first oxide layer can be removed, and an interlayer dielectric layer can be deposited.