Abstract: A nonvolatile memory module includes a plurality of volatile memory devices sharing a data bus through which data is transmitted and a control bus through which a command and an address are transmitted; at least one nonvolatile memory device; and a controller including a backup logic which backs up data stored in the plurality of volatile memory devices when a fail in power of the host is detected or a backup operation is instructed from the memory controller of the host, wherein the backup logic sets a command address latency (CAL) of one among the plurality of volatile memory devices to a first value, and sets a command address latency of remaining volatile memory devices to a second value different from the first value.

Abstract: A nonvolatile memory module includes volatile memory devices; a nonvolatile memory device; and a controller suitable for backing up data stored in the volatile memory devices or restoring data backed up in the nonvolatile memory device, according to a fail/recovery of power of the host, the controller including a power-down interrupt logic which interrupts a backup operation when the power of the host is recovered while performing the backup operation, the power-down interrupt logic including: a logic which determines whether sufficient erased blocks exist in the nonvolatile memory device; a logic which erases a new block when the sufficient erased bocks do not exist; and an interrupt backup logic which backs up a volatile memory device having data corresponding to the erased block, when a fail in the power of the host is detected or a backup operation is instructed from the host.

Abstract: A nonvolatile memory module includes volatile memory devices sharing a data bus and a control bus; at least one nonvolatile memory device; and a controller for backing up data stored in the volatile memory devices into the nonvolatile memory device at a power failure of a host, and restoring data backed up in the nonvolatile memory device to the volatile memory devices at recovery of the power failure, the controller including: a command/address snooping logic for snooping on a command and an address inputted from a memory controller of the host, and analyzing amounts of stored data in the respective volatile memory devices; and a command/address control logic for selecting one of the volatile memory devices in order of the amounts of stored data based on analysis results of the command/address snooping logic, and backing up data of the selected volatile memory device in the nonvolatile memory device.

Abstract: A nonvolatile memory module includes volatile memory devices sharing a data bus and a control bus through which a command and an address are transmitted; at least one nonvolatile memory device; and a controller for backing up data stored in the volatile memory devices into the nonvolatile memory device at a power failure of a host, and restoring data backed up in the nonvolatile memory device to the volatile memory devices at recovery of the power failure, the controller including: a command/address snooping logic for snooping on a command and an address inputted from a memory controller of the host, and analyzing valid areas of data stored in the respective volatile memory devices; and a command/address control logic for selecting the volatile memory device having the valid area of data based on analysis results of the command/address snooping logic, and backing up selected volatile memory into the nonvolatile memory device.

Abstract: A nonvolatile memory module includes a plurality of volatile memory devices sharing a data bus through which data is transmitted and a control bus through which a command and an address are transmitted; at least one nonvolatile memory device; and a controller including a backup logic which backs up data stored in the plurality of volatile memory devices when a fail in power of the host is detected or a backup operation is instructed from the memory controller of the host, wherein the backup logic sets a command address latency (CAL) of one among the plurality of volatile memory devices to a first value, and sets a command address latency of remaining volatile memory devices to a second value different from the first value.

Abstract: A nonvolatile memory module includes volatile memory devices; a nonvolatile memory device; and a controller suitable for backing up data stored in the volatile memory devices or restoring data backed up in the nonvolatile memory device, according to a fail/recovery of power of the host, the controller including a power-down interrupt logic which interrupts a backup operation when the power of the host is recovered while performing the backup operation, the power-down interrupt logic including: a logic which determines whether sufficient erased blocks exist in the nonvolatile memory device; a logic which erases a new block when the sufficient erased bocks do not exist; and an interrupt backup logic which backs up a volatile memory device having data corresponding to the erased block, when a fail in the power of the host is detected or a backup operation is instructed from the host.

Abstract: A nonvolatile memory module includes volatile memory devices sharing a data bus and a control bus; at least one nonvolatile memory device; and a controller for backing up data stored in the volatile memory devices into the nonvolatile memory device at a power failure of a host, and restoring data backed up in the nonvolatile memory device to the volatile memory devices at recovery of the power failure, the controller including: a command/address snooping logic for snooping on a command and an address inputted from a memory controller of the host, and analyzing amounts of stored data in the respective volatile memory devices; and a command/address control logic for selecting one of the volatile memory devices in order of the amounts of stored data based on analysis results of the command/address snooping logic, and backing up data of the selected volatile memory device in the nonvolatile memory device.

Abstract: A method for testing a memory device includes entering a test mode in which multiple memory banks operate in a same manner, allowing a row corresponding to a row address in the multiple memory banks to be activated, latching a bank address and the row address corresponding to the multiple memory banks, writing same data in a column selected by a column address in the multiple memory banks, reading the data written in the writing of the data from the multiple memory banks, checking whether the data read from the multiple memory banks in the reading of the data are equal to each other, and programming the bank address and the row address to a nonvolatile memory when the data read from the multiple memory banks are different from each other.

Abstract: A method for testing a memory device includes entering a test mode in which multiple memory banks operate in a same manner, allowing a row corresponding to a row address in the multiple memory banks to be activated, latching a bank address and the row address corresponding to the multiple memory banks, writing same data in a column selected by a column address in the multiple memory banks, reading the data written in the writing of the data from the multiple memory banks, checking whether the data read from the multiple memory banks in the reading of the data are equal to each other, and matching the memory bank address and the row address with each other and programming the matched address to a nonvolatile memory when the data read from the multiple memory banks are different from each other.