Abstract: A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.

Abstract: A semiconductor device comprises a substrate including NMOSFET and PMOSFET regions, first and second channel patterns on the NMOSFET and PMOSFET regions, respectively, and each including respective semiconductor patterns spaced apart from and vertically stacked on each other, first and second source/drain patterns on the NMOSFET and NMOSFET regions and connected to the first and second channel patterns, respectively, and a gate electrode on the first and second channel patterns. The gate electrode includes a first inner electrode between neighboring semiconductor patterns of the first channel pattern, and a second inner electrode between neighboring semiconductor patterns of the second channel pattern. A top surface of the first inner electrode is more convex than a top surface of the second inner electrode.

Abstract: A semiconductor device may include a first active fin, a second active fin and a gate structure. The first active fin may extend in a first direction on a substrate and may include a first straight line extension portion, a second straight line extension portion, and a bent portion between the first and second straight line extension portions. The second active fin may extend in the first direction on the substrate. The gate structure may extend in a second direction perpendicular to the first direction on the substrate. The gate structure may cross one of the first and second straight line extension portions of the first active fin and may cross the second active fin.

Abstract: A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

Abstract: A semiconductor device includes a lower pattern extending in a first direction and sheet patterns spaced apart therefrom in a second direction, a gate structure on the lower pattern and including a gate insulating layer, a gate spacer, and a gate electrode, a source/drain pattern on the lower pattern and in contact with the sheet patterns and the gate insulating layer, and a first etch blocking pattern between the gate spacer and the source/drain pattern. The gate spacer includes an inner sidewall extending in the third direction, and a connection sidewall extending from the inner sidewall in the first direction. The source/drain pattern includes a semiconductor filling layer on a semiconductor liner layer that is in contact with the sheet pattern and includes a facet surface extending from the connection sidewall. The first etch blocking pattern is in contact with the facet surface and the connection sidewall.

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns, and a gate dielectric layer between the gate electrode and the semiconductor patterns. An inner spacer of the gate dielectric layer includes a horizontal portion between the high-k dielectric layer and the second semiconductor pattern, a vertical portion between the high-k dielectric layer and the source/drain pattern, and a corner portion between the horizontal portion and the vertical portion. A first thickness of the horizontal portion is less than a second thickness of the vertical portion. The second thickness of the vertical portion is less than a third thickness of the corner portion.

Abstract: A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.

Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.

Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.

Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.

Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.

Abstract: A simulation method includes storing a plurality of structure parameters of transistors for a semiconductor chip, imaging generating a first local layout which includes a first structure parameter extracted from a semiconductor device included in the first local layout, the first structure parameter being an actual parameter determined using the imaging equipment, generating second to n-th local layouts by modifying the first structure parameter included in the first local layout, wherein the second to n-th local layouts respectively have second to n-th structure parameters modified from the first structure parameter, calculating first to n-th effective density factors (EDF) respectively for the first to n-th structure parameters, determining a first effective open silicon density for a first chip using the first to n-th effective density factors and a layout of the first chip, and calculating first to m-th epitaxy times for first to m-th effective open silicon densities.

Abstract: A semiconductor device may include a first active fin, a second active fin and a gate structure. The first active fin may extend in a first direction on a substrate and may include a first straight line extension portion, a second straight line extension portion, and a bent portion between the first and second straight line extension portions. The second active fin may extend in the first direction on the substrate. The gate structure may extend in a second direction perpendicular to the first direction on the substrate. The gate structure may cross one of the first and second straight line extension portions of the first active fin and may cross the second active fin.

Abstract: A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.

Abstract: A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

Abstract: A simulation method and system which can determine a predictable epitaxy time by accurately reflecting layout characteristics of a chip and characteristics of a source/drain formation process are provided.

Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.