Patents by Inventor Hyun Kwang JEONG

Hyun Kwang JEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210265337
    Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.
    Type: Application
    Filed: May 12, 2021
    Publication date: August 26, 2021
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Kyong Jin HWANG, Hyun Kwang JEONG
  • Patent number: 11043483
    Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 22, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Kyong Jin Hwang, Hyun Kwang Jeong
  • Publication number: 20180358349
    Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 13, 2018
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Kyong Jin HWANG, Hyun Kwang JEONG
  • Patent number: 10068892
    Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 4, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Kyong Jin Hwang, Hyun Kwang Jeong
  • Publication number: 20170294431
    Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.
    Type: Application
    Filed: June 19, 2017
    Publication date: October 12, 2017
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Kyong Jin HWANG, Hyun Kwang Jeong
  • Patent number: 9721941
    Abstract: The present examples relate to a semiconductor chip having a level shifter with an electrostatic discharge (ESD) protection circuit and a device applying to multiple power supply lines with high and low power inputs to protect the level shifter from the static ESD stress. More particularly, the present examples relate to using a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device itself.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: August 1, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Kyong Jin Hwang, Hyun Kwang Jeong
  • Publication number: 20160268251
    Abstract: The present examples relate to a semiconductor chip having a level shifter with an electrostatic discharge (ESD) protection circuit and a device applying to multiple power supply lines with high and low power inputs to protect the level shifter from the static ESD stress. More particularly, the present examples relate to using a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device itself.
    Type: Application
    Filed: July 20, 2015
    Publication date: September 15, 2016
    Applicant: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventors: Kyong Jin HWANG, Hyun Kwang JEONG