Abstract: This application relates to a pellicle for extreme ultraviolet lithography and a manufacturing method thereof using the low-temperature direct growth method of multilayer graphene. In one aspect, the method includes forming an etch stopper on a substrate, forming a seed layer on the etch stopper, the seed layer including at least one of amorphous boron, BN, BCN, B4C, or Me-X (Me is at least one of Si, Ti, Mo, or Zr, and X is at least one of B, C, or N). The method may also include forming a metal catalyst layer on the seed layer; forming an amorphous carbon layer on the metal catalyst layer, and directly growing multilayer graphene on the seed layer through interlayer exchange between the metal catalyst layer and the amorphous carbon layer by performing a low-temperature heat treatment at 450° C. to 600° C.

Abstract: This application relates to a pellicle for extreme ultraviolet lithography based on yttrium (Y) and used in a lithography process using extreme ultraviolet rays. In one aspect, the pellicle includes a pellicle layer including a core layer formed of an yttrium-based material expressed as Y-M (M is one of B, Si, O, or F).

Abstract: This application relates to a method for direct growth of multilayer graphene used as a core layer of a pellicle for extreme ultraviolet lithography. This application also relates to a method for manufacturing the pellicle for extreme ultraviolet lithography by using the multilayer graphene direct growth method. The multilayer graphene direct growth method may include forming few-layer graphene on a silicon nitride substrate, forming a metal catalyst layer on the few-layer graphene, and forming an amorphous carbon layer on the metal catalyst layer. The method may also include directly growing multilayer graphene from the few-layer graphene used as a seed layer by interlayer exchange between the metal catalyst layer and the amorphous carbon layer through heat treatment.

Abstract: Provided is an artificial neural network processing apparatus including: first to fourth submatrix multiplication operators configured to perform a first submatrix multiplication operation and then a second submatrix multiplication operation using eight pieces of input data; a memory mapping unit configured to map at least a portion of the eight pieces of input data to the first to fourth submatrix multiplication operators with a first mapping structure for the first submatrix multiplication operation, and map at least a portion of the eight pieces of input data to the first to fourth submatrix multiplication operators with a second mapping structure for the second submatrix multiplication operation, wherein the first mapping structure and the second mapping structure have different mapping structures; and a controlling unit configured to control the memory mapping unit to be formed with the first mapping structure or the second mapping structure.

Abstract: A reorganizable neural network computing device is provided. The computing device includes a data processing array unit including a plurality of operators disposed at locations corresponding to a row and a column. One or more chaining paths which transfer the first input data from the operator of the first row of the data processing array to the operator of the second row are optionally formed. The plurality of first data input processors of the computing device transfer the first input data for a layer of the neural network to the operators along rows of the data processing array unit, and the plurality of second data input processors of the computing device transfer the second input data to the operators along the columns of the data processing array.

Abstract: A nanoscale thin film structure and implementing method thereof, and, more specifically, a nanoscale thin film structure of which target structure is designed with quantized thickness, and a method to implement the nanoscale thin film structure by which the performance of the manufactured nanodevice can be implemented the same as the designed performance, thereby applicable to high sensitivity high performance electronic/optical sensor devices.

Abstract: Disclosed herein are an apparatus and method for managing cache memory. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program reads an s1-tag and an s2-tag of cache memory upon receiving an access request address for reading data in response to a request to access the cache memory, checks whether the access request address matches the value of the s1-tag and the value of the s2-tag, and reads the data from data memory when the access request address matches all of the value of the s1-tag and the value of the s2-tag.

Abstract: Disclosed herein are a prefetching device and method for an artificial intelligence processor. The prefetching method includes prefetching data, stored in external off-chip memory, into internal on-chip memory in the artificial intelligence processor, and storing information including an address value and a total amount of matrix operation data in at least one control and status register, as a kernel program is executed, extracting a matrix operation instruction among instructions provided from an instruction cache of the off-chip memory, determining whether prefetching is enabled based on a result of extracting the matrix operation instruction, as prefetching is enabled, determining a number of blocks to be prefetched based on the information stored in the at least one control and status register, and determining a bus burst value corresponding to the determined number of blocks and transmitting the bus burst value as a data request signal through a bus interface.

Abstract: A pellicle for extreme ultraviolet (EUV) lithography is based on yttrium carbide and used in a EUV lithography process. The pellicle for EUV lithography includes a pellicle layer that has a core layer containing yttrium carbide. The yttrium carbide is YCx in which the atomic percentage of carbon is within a range of 25% to 45%.

Abstract: Disclosed is a parallel processor. The parallel processor includes a processing element array including a plurality of processing elements arranged in rows and columns, a row memory group including row memories corresponding to rows of the processing elements, a column memory group including column memories corresponding to columns of the processing elements, and a controller to generate a first address and a second address, to send the first address to the row memory group, and to send the second address to the column memory group. The controller supports convolution operations having mutually different forms, by changing a scheme of generating the first address.

Abstract: This application relates to a method for manufacturing a pellicle for extreme ultraviolet lithography. In one aspect, the method includes forming a support layer of a silicon nitride material on a silicon substrate, and forming a core layer of a graphene material on the support layer. The method may also include forming a graphene defect healing layer on the core layer by selectively forming a material of MeOxNy (Me is one of Si, Al, Ti, Zr, and Hf, x+y=2) at a grain boundary of the core layer in an atomic layer deposition process using heat in order to heal defects generated in graphene forming the core layer without additional damage to the graphene. The method may further include a capping layer on the graphene defect healing layer, wherein a central portion of the silicon substrate under the support layer is removed to form an opening partially exposing the support layer.

Abstract: Disclosed herein is a method for outer-product-based matrix multiplication for a floating-point data type includes receiving first floating-point data and second floating-point data and performing matrix multiplication on the first floating-point data and the second floating-point data, and the result value of the matrix multiplication is calculated based on the suboperation result values of floating-point units.

Abstract: Proposed is a data parallel processing method for a recurrent neural network in a neural network accelerator based on a systolic array. A data processing device receives voice data of a user in a predetermined time section. The data processing device generates a plurality of voice data units by separating the voice data by sentence. The data processing device generates a plurality of input vectors by vectorizing the plurality of voice data units. The data processing device inputs the plurality of input vectors to a neural network accelerator based on a systolic array. In this manner, the data is processed.

Abstract: A pellicle for extreme ultraviolet (EUV) lithography is based on yttrium carbide and used in a EUV lithography process. The pellicle for EUV lithography includes a pellicle layer that has a core layer containing yttrium carbide. The yttrium carbide is YCX (0.25<x<0.45).

Abstract: Disclosed herein are an apparatus and method for managing cache memory. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program reads an s1-tag and an s2-tag of cache memory upon receiving an access request address for reading data in response to a request to access the cache memory, checks whether the access request address matches the value of the s1-tag and the value of the s2-tag, and reads the data from data memory when the access request address matches all of the value of the s1-tag and the value of the s2-tag.

Abstract: The present disclosure relates to a single nucleic acid for real-time detection for SNP analysis of apolipoprotein E (ApoE) gene and a detection method using the same. More specifically, the present disclosure relates to a method of detecting in real time single nucleotide polymorphisms of ApoE gene by the use of a single nucleic acid, which has a structure of X-Y-Z and consists of a nucleotide sequence capable of complementary binding to a portion or all of the nucleotide sequence of the ApoE gene showing single nucleotide polymorphisms, and a kit therefor.

Abstract: The present invention relates to a method for manufacturing a sample for thin film property measurement and analysis, and a sample manufactured thereby and, more specifically, to: a method for manufacturing a sample capable of measuring or analyzing various properties in one sample; and a sample manufactured thereby.

Abstract: Provided is a neural network accelerator which performs a calculation of a neural network provided with layers, the neural network accelerator including a kernel memory configured to store kernel data related to a filter, a feature map memory configured to store feature map data which are outputs of the layers, and a Processing Element (PE) array including PEs arranged along first and second directions, wherein each of the PEs performs a calculation using the feature map data transmitted in the first direction from the feature map memory and the kernel data transmitted in the second direction from the kernel memory, and transmits a calculation result to the feature map memory in a third direction opposite to the first direction.

Abstract: This application relates to a pellicle for extreme ultraviolet lithography used in a lithography process using extreme ultraviolet rays. In one aspect, the pellicle includes a pellicle layer formed of an M-? material in which M is combined with ?. Here, M is one of Si, Zr, Mo, Ru, Y, W, Ti, Ir, or Nb, and a is at least two of B, N, C, O, or F.

Abstract: This application relates to a pellicle for extreme ultraviolet lithography containing amorphous carbon and a manufacturing method thereof. In one aspect, the pellicle includes a substrate having an opening formed in a central portion, a support layer formed on the substrate to cover the opening, and a pellicle layer formed on the support layer and containing amorphous carbon. The pellicle layer may include a core layer formed on the support layer, and a capping layer formed on the core layer and may further include a buffer layer. At least one of the core layer, the capping layer, or the buffer layer may be an amorphous carbon layer.