Abstract: A neural network device for performing a neural network operation includes a floating point arithmetic circuit configured to perform a dot-product operation for each of a plurality of floating point data pairs, wherein the floating point arithmetic circuit is configured to, in the dot-product operation, align-shift a plurality of fraction part multiplying operation results respectively corresponding to the floating point data pairs based on a maximum value determined from a plurality of exponent part adding operation results respectively corresponding to the floating point data pairs.

Abstract: A neural network device includes a calculation circuit that includes a first multiplier, a second multiplier, an align shifter, and an adder. The adder shares the first multiplier and the second multiplier. The calculation circuit performs a first dot product operation on a plurality of floating point data pairs or a second dot product operation on a plurality of integer data pairs. In the first dot product operation, the calculation circuit obtains a plurality of fraction multiplication results from the plurality of floating point data pairs, respectively, using the first multiplier, adds the plurality of fraction multiplication results using the adder and outputs first cumulative data. In the second dot product operation, the calculation circuit obtains a plurality of integer multiplication results from the plurality of integer data pairs, respectively, using the second multiplier, adds the plurality of integer multiplication results using the adder, and outputs second cumulative data.

Abstract: According to the present disclosure, a network protection device includes: a communication device; a storage device configured to store a white list that defines access rights between a plurality of first terminals belonging to a target network; and a control device configured to modulate an address resolution protocol (ARP) table of each of the plurality of first terminals using an ARP packet so that a first communication flow generated between the plurality of first terminals is received by the communication device, and block the first communication flow or transmit the first communication flow to a destination based on the white list when the first communication flow is received.

Abstract: A neural network device includes a floating-point arithmetic circuit configured to perform a dot product operation and an accumulation operation; and a buffer configured to store first cumulative data generated by the floating-point arithmetic circuit, wherein the floating-point arithmetic circuit is further configured to perform the dot product operation and the accumulation operation by: identifying a maximum value from a plurality of exponent addition results, obtained by respectively adding exponents of a plurality of floating-point data pairs, and an exponent value of the first cumulative data; performing, based on the maximum value, an align shift of a plurality of fraction multiplication results, obtained by respectively multiplying fractions of the plurality of floating-point data pairs, and a fraction part of the first cumulative data; and performing a summation of the plurality of aligned fraction multiplication results and the aligned fraction part of the first cumulative data.

Abstract: A processor includes a register file, a context controller that, in response to a target interrupt occurring, is configured to determine, a target register that stores new data acquired through each of commands for executing an interrupt service routine (ISR) among the plurality of registers, a write buffer configured to transmit pre-data stored in the target register to a memory, and a flag register configured to store set data including set values indicating whether the new data is stored in each of the registers. The context controller is configured to determine whether to transfer the pre-data to the memory through the write buffer based on the set data.

Abstract: An in-order processor using a multiple-issue scheme includes a control unit configured to fetch a plurality of instructions together, to determine whether to multiple-issue the plurality of fetched instructions, to decode an issued instruction based on the determination, and to determine whether a stall of the decoded instruction is caused by a data hazard. The processor further includes an execution unit configured to execute an instruction transmitted from the control unit, and a buffer configured to store stall history information on a plurality of multiple-issued instructions when the plurality of multiple-issued instructions are stalled by the data hazard. The control unit determines whether to multiple-issue the plurality of fetched instructions, based on the stall history information of the buffer.

Abstract: An electronic device includes a communication interface operable to perform contactless communication with an external device; and a processor operable to control to determine a communication type to be performed with the external device; when the communication type is a first type of continuous communication, configure data in a long packet structure; when the communication type is a second type of discontinuous communication, configure data in a short packet structure; and perform data communication in the continuous communication or in the discontinuous communication with the external device on the basis of the determined communication type.

Abstract: A neural network device for performing a neural network operation includes a floating point arithmetic circuit configured to perform a dot-product operation for each of a plurality of floating point data pairs, wherein the floating point arithmetic circuit is configured to, in the dot-product operation, align-shift a plurality of fraction part multiplying operation results respectively corresponding to the floating point data pairs based on a maximum value determined from a plurality of exponent part adding operation results respectively corresponding to the floating point data pairs.

Abstract: A neural network device includes a calculation circuit that includes a first multiplier, a second multiplier, an align shifter, and an adder. The adder shares the first multiplier and the second multiplier. The calculation circuit performs a first dot product operation on a plurality of floating point data pairs or a second dot product operation on a plurality of integer data pairs. In the first dot product operation, the calculation circuit obtains a plurality of fraction multiplication results from the plurality of floating point data pairs, respectively, using the first multiplier, adds the plurality of fraction multiplication results using the adder and outputs first cumulative data. In the second dot product operation, the calculation circuit obtains a plurality of integer multiplication results from the plurality of integer data pairs, respectively, using the second multiplier, adds the plurality of integer multiplication results using the adder, and outputs second cumulative data.

Abstract: A neural network device includes a floating-point arithmetic circuit configured to perform a dot product operation and an accumulation operation; and a buffer configured to store first cumulative data generated by the floating-point arithmetic circuit, wherein the floating-point arithmetic circuit is further configured to perform the dot product operation and the accumulation operation by: identifying a maximum value from a plurality of exponent addition results, obtained by respectively adding exponents of a plurality of floating-point data pairs, and an exponent value of the first cumulative data; performing, based on the maximum value, an align shift of a plurality of fraction multiplication results, obtained by respectively multiplying fractions of the plurality of floating-point data pairs, and a fraction part of the first cumulative data; and performing a summation of the plurality of aligned fraction multiplication results and the aligned fraction part of the first cumulative data.

Abstract: An electronic device includes a communication interface operable to perform contactless communication with an external device; and a processor operable to control to determine a communication type to be performed with the external device; when the communication type is a first type of continuous communication, configure data in a long packet structure; when the communication type is a second type of discontinuous communication, configure data in a short packet structure; and perform data communication in the continuous communication or in the discontinuous communication with the external device on the basis of the determined communication type.

Abstract: A continuous communication apparatus includes a communication interface configured for contactless communication with a different electronic device; and a processor configured to detect a trigger to initiate contactless communication with the different electronic device; determine a communication type associated with communication to be performed with the different electronic device upon detecting the trigger; set at least one parameter associated with continuous communication when the communication type is the continuous communication; and perform the continuous communication with the different electronic device on the basis of the configured parameter.

Abstract: A continuous communication apparatus includes a communication interface configured for contactless communication with a different electronic device; and a processor configured to detect a trigger to initiate contactless communication with the different electronic device; determine a communication type associated with communication to be performed with the different electronic device upon detecting the trigger; set at least one parameter associated with continuous communication when the communication type is the continuous communication; and perform the continuous communication with the different electronic device on the basis of the configured parameter.

Abstract: Methods and apparatuses for performing arithmetic operations efficiently and quickly are described. Such arithmetic operations include, but are not limited to, multiplying 2N bit integers, multiplying multiple N-bit integers simultaneously, multiplying 2N bit complex numbers, and other multiplication operations involving coefficients, complex numbers, and complex conjugate numbers.

Abstract: Methods and apparatuses for performing arithmetic operations efficiently and quickly are described. Such arithmetic operations include, but are not limited to, multiplying 2N bit integers, multiplying multiple N-bit integers simultaneously, multiplying 2N bit complex numbers, and other multiplication operations involving coefficients, complex numbers, and complex conjugate numbers.