Abstract: A method of fabricating a memory device for improving the reliability of the cell area and the driving capability of the peripheral area is disclosed, wherein the method comprises the steps of forming a cell area and a peripheral area by forming a field oxidation layer over a first conductive semiconductor substrate, forming gate oxidation layers of the different thickness from each other over a surface of the substrate which corresponds to the cell area and the peripheral area through once oxidation process, forming a gate over the gate oxidation layer, and implanting a second conductive impurity ion into the substrate partly covered with the gates as a mask to form highly-doped source/drain areas in the respective cell and peripheral area, thereby forming respective MOS transistors on each of the cell area and the peripheral area.

Abstract: A method of fabricating a nonvolatile memory device including the steps of depositing a first oxide film by chemical vapor deposition over a semiconductor substrate of a first conductivity type; applying a photo etching process to the first oxide film so as to expose a portion of the semiconductor substrate; forming a gate oxide film on the exposed portion of the semiconductor substrate; coating in sequence a first polysilicon film, an insulating film, and a second polysilicon film entirely over the resultant structure; applying an etchback process to the first polysilicon film, the insulating film, and the second polysilicon film so as to form an EEPROM structure, which includes a floating gate at a sidewall of the first oxide film, the insulating film being used as an interlayer insulating film, and a control gate, the floating gate having two regions integrally formed with one region lying flat over the gate oxide film in a first direction and the other region extending from an end portion of the first reg

Abstract: A method of fabricating a nonvolatile semiconductor memory device so as to improve interface properties between a tunneling oxide layer and a floating gate of the nonvolatile semiconductor memory device is disclosed, wherein the method comprises the steps of forming a tunneling oxide layer on a substrate, forming a floating gate consisting of a plurality of thin silicon layers which are formed through the repeated cyclical process under the low temperature of around 550 degrees C., forming an interposed insulating layer over a whole surface of the floating gate by a selective etching process of the silicon layers; and forming a control gate over a whole surface of the interposed insulating layer.

Abstract: A process for the fabrication of an MOS transistor.The process comprises the steps of forming a gate oxide film on a substrate, forming a p.sup.+ polysilicon film doped with p type impurity ions over said gate oxide film, coating an insulating film and a photoresist film over said p.sup.+ polysilicon film, in sequence, subjecting the resultant structure to a patterning to expose a portion of said insulating film, applying an etching method to said exposed insulating film with said photoresist film used as a mask, implanting fluorine ions in said p.sup.+ polysilicon film with resultant insulating film used as a mask, removing the remaining photoresist film, carrying out an annealing method to form a low density p.sup.- source/drain regions, applying an etching method to said p.sup.

Abstract: A method for fabricating an asymmetry HS-GOLD MOSFET by use of a photo etch process in place of a large tilt implantation process, capable of improving a packing density and reducing a junction capacitance of a source region, thereby improving a characteristic of a device to be finally produced. The method includes the steps of forming a gate insulating film and a gate on a p.sup.- type semiconductor substrate, implanting n type impurity ions in the semiconductor substrate so as to symmetrically form n.sup.- type source and drain regions in the semiconductor substrate, forming an insulating film over the entire exposed surface of the resulting structure, subjecting the insulating to an anisotropic etching to form spacers at respective side walls of the gate, implanting n type impurity ions in the semiconductor substrate so as to form n.sup.+ type high concentration source and drain regions respectively adjacent to the n.sup.