Abstract: Disclosed are an oxidizing electrode, a water electrolysis device including the same and a method for manufacturing the same. According to exemplary embodiments of the present disclosure, there is provided an oxidizing electrode with improved performance at low loadings of noble metals, especially, ruthenium (Ru) and iridium oxide, in which a ruthenium (Ru) layer and an iridium oxide layer formed on a substrate by electrodeposition in a sequential order are supported by electrochemical reaction rather than physical bonding.

Abstract: A reprogrammable programmable logic array comprising a first write module for inputting data to be written and data to be compared, an AND CAM cell array block for, in a write mode, sequentially storing the write data from the first write module and, in a match mode, comparing the comparison data from the first write module with its pre-stored data and generating match signals in accordance with the compared result, a first address module for, in the write mode, generating sequential addresses and supplying the generated sequential addresses to the AND CAM cell array block, a second write module for inputting data to be written in the write mode, an OR CAM cell array block for storing sequentially the write data from the second write module in the write mode and detecting its pre-stored data corresponding to the match signals from the AND CAM cell array block in the match mode, a second address module for, in the write mode, generating sequential addresses and supplying the generated sequential addresses to t

Abstract: A high-speed carry increment adding device having a first module including a first adder, the first adder adding a desired number of first bit inputs and generating a plurality of partitioned sums and a partitioned carry as a result of the addition, and a second module including a second adder and a conditional incrementer, the second adder adding a desired number of second bit inputs regardless of the partitioned carry from the first adder and generating a plurality of partitioned sums and a partitioned carry as a result of the addition, the conditional incrementer inputting the partitioned carry from the first adder as an increment signal and incrementing the partitioned sums from the second adder in response to the inputted increment signal. Also, the second module includes a partitioned sum detector for detecting whether all of the partitioned sums from the second adder are "1" and generating a partitioned sum detect signal in accordance with the detected result.

Abstract: A phase locked loop circuit comprising a first counter for dividing a reference frequency at a division ratio predetermined or determined by an input unit, a second counter for dividing a frequency of an output signal from the phase locked loop circuit at a division ratio predetermined or determined by a different input unit, a phase detector for inputting output signals from the first and second counters and generating a voltage based on a phase difference between the inputted signals, a low pass filter for low pass filtering an output signal from the phase detector, and a voltage controlled oscillator for generating a frequency signal proportioned to an output voltage from the low pass filter. The phase locked loop circuit further comprises an unlock detector for generating a control signal for synchronization of one of the first and second counters with an earlier phase in response to an unlocked signal from the phase detector.

Abstract: A 2's complementer having a simple circuit arrangement and yet obtaining a high 2's-complementation rate. The 2's complementer includes an inverting circuit for inverting binary data with at least two bits to produce an 1's complement. The 2's complementer also includes an inverter for inverting inverted data resulted from an inversion of the least-significant bit of the 1's-complement data of at least two bits, and at least one exclusive OR gate for comparing bit data to be currently processed with lower-order bit data of at least one bit of the 1's-complement data, and inverting the current bit data when the at least one lower-order bit data has the value of logic-1.

Abstract: A power-on reset circuit is disclosed comprising a capacitor for being charged to a desired voltage and then being discharged; a Schmitt trigger circuit for discriminating the voltage discharged from the capacitor and transitioning instantaneously its output when the discharged voltage reaches a predetermined level to output a reset signal, and then transitioning its output again after the lapse of a predetermined time period to maintain a constant voltage; a state latch circuit for inputting the output of the Schmitt trigger circuit, the state latch circuit being transitioned after the lapse of a predetermined time period from generation of the reset signal by the Schmitt trigger circuit and then remaining at the transitioned state; and an inverter for inverting an output voltage of the state latch circuit and applying the inverted output voltage to the capacitor.