Abstract: An operating method of a memory device, comprises: a program operation of applying a program voltage to a selected word line to program selected memory cells connected to the selected word line, a first verification operation of applying a first verification voltage to the selected word line and applying a first verification pass voltage to unselected word lines to verify a first program state of the selected memory cells, and a second verification operation of applying a second verification voltage to the selected word line and applying a second verification pass voltage to the unselected word lines to verify a second program state higher than the first program state.

Abstract: A memory device includes: a memory cell array including a first memory cell group including memory cells located within a first physical distance from a reference node and a second memory cell group including memory cells located beyond the first physical distance from the reference node; a peripheral circuit configured to perform a program operation of applying program voltages increasing gradually to memory cells included in the memory cell array through word lines; and control logic configured to determine a time at which a first program permission voltage is applied to the first memory cell group and determine a magnitude of the first program permission voltage on the basis of a magnitude of the program voltages in response to a gradual increase in the program voltages, the control logic is further configured to control the peripheral circuit to apply the first program permission voltage to the first memory cell group through bit lines.

Abstract: A memory device includes a plurality of memory cells, where each memory cell is configured to be in an erased state or one of a plurality of program states according to data stored therein. The memory device also includes a peripheral circuit configured to, in a program operation on the plurality of memory cells, perform a first program voltage application operation on first memory cells, the first memory cells being to be programmed to first respective program states. The peripheral circuit is also configured to perform, after the first program voltage application operation, a pre-program voltage application operation on second memory cells, the second memory cells being to be programmed to second respective program states.

Abstract: A memory device including: a memory block including a word lines, word lines located in the middle of the word lines are used as dummy word lines, a control circuit establish word lines stacked on one side and other side of the dummy word lines into a first and second sub-blocks, respectively, performs an independent erase operation on one of the first and second sub-blocks in an erase operation period, and a control logic differently sets a level of a first transfer voltage for controlling transfer of an erase common voltage to the selected sub-block and the level of a second transfer voltage for controlling transfer of the erase common voltage to the unselected sub-block, applies an erase allowable voltage from the erase common voltage to a word line of the selected sub-block, and floats a word line of the unselected sub-block, in the erase operation period.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a program operation performer configured to perform a plurality of program loops on the plurality of memory cells, a step voltage calculator configured to calculate a step voltage, the step voltage being a difference of magnitude between program voltages that are applied in any two consecutive program loops, a reference bit determiner configured to determine a reference number of fail bits based on a magnitude of the step voltage, and a verification result generator configured to generate verification result information based on a result of a comparison between the reference number of fail bits and a number of on-cells, among the plurality of memory cells, identified in a verify operation that is included in a program loop, among the plurality of program loops.

Abstract: A memory device includes: a plurality of memory cells; a peripheral circuit for performing a program operation including a plurality of loops each including a program voltage apply step and a verify step by using a plurality of verify voltages; and a program operation controller for controlling the peripheral circuit to perform the program operation. The program operation controller includes: a verify voltage controller for changing a verify voltage interval as an interval between the plurality of verify voltages from a predetermined target loop among the plurality of loops; and a bit line voltage controller to control bit line voltages applied to bit lines connected to first memory cells and second memory cells in the program voltage apply steps of an (n+1)th loop and an (n+2)th loop, based on a verify result in the verify step of an nth loop among the plurality of loops.

Abstract: An operating method of a memory device, comprises: a program operation of applying a program voltage to a selected word line to program selected memory cells connected to the selected word line, a first verification operation of applying a first verification voltage to the selected word line and applying a first verification pass voltage to unselected word lines to verify a first program state of the selected memory cells, and a second verification operation of applying a second verification voltage to the selected word line and applying a second verification pass voltage to the unselected word lines to verify a second program state higher than the first program state.

Abstract: A memory device including: a memory block including a word lines, word lines located in the middle of the word lines are used as dummy word lines, a control circuit establish word lines stacked on one side and other side of the dummy word lines into a first and second sub-blocks, respectively, performs an independent erase operation on one of the first and second sub-blocks in an erase operation period, and a control logic differently sets a level of a first transfer voltage for controlling transfer of an erase common voltage to the selected sub-block and the level of a second transfer voltage for controlling transfer of the erase common voltage to the unselected sub-block, applies an erase allowable voltage from the erase common voltage to a word line of the selected sub-block, and floats a word line of the unselected sub-block, in the erase operation period.