Abstract: A semiconductor device includes a repeater configured to output latch data as aligned data when the operation control signal is disabled and configured to interrupt the input of the latch data when the operation control signal is enabled for performing a data masking operation of internal data. The operation control signal is enabled according to logic levels of the internal data when a flag signal is enabled and a write data control signal is enabled.

Abstract: A semiconductor memory apparatus may include a data control circuit, an input/output circuit block, and a data line repeater block. The data control circuit may generate a data control flag signal based on an operation control signal and data. The input/output circuit block may perform a data bus inversion operation for the data, based on the data control flag signal. The data line repeater block may perform a data masking operation for the data based on the data control flag signal.

Abstract: A non-aqueous electrolyte solution for a lithium secondary battery, and a lithium second battery including the same are disclosed herein. In some embodiments, the lithium eletrotrolyte includes lithium bis(fluorosulfonyl)imide as a first lithium salt, a second lithium salt, an organic solvent, and a compound represented by Formula 1. In some embodiments, the lithium second battery includes a positive electrode having a positive electrode active material represented by Formula 2.

Abstract: A non-aqueous electrolyte solution for a lithium secondary battery and a lithium secondary battery including the same are disclosed herein. In an embodiment, the electrolyte solution includes a lithium salt, an organic solvent, a compound represented by Formula 1 as a first additive, lithium difluorophosphate (LiDFP) as a second additive, wherein the first additive and the second additive are each independently included in an amount of 0.01 wt % to 8.5 wt % based on a total amount of the non-aqueous electrolyte solution. The first additive has metal ion adsorbability and is capable of forming a stable ion conductive film on the surface of an electrode, and a lithium secondary battery in which an abnormal voltage drop phenomenon is improved by including the same.

Abstract: A semiconductor device includes a synthesis control signal generation circuit and a data output control circuit. The synthesis control signal generation circuit generates a synthesis control signal for determining a burst sequence from a latch control signal in response to a first burst mode command and a second burst mode command. The data output control circuit outputs data included in a bank group as internal data in response to the synthesis control signal.

Abstract: The present invention relates to a non-aqueous electrolyte solution additive, and a non-aqueous electrolyte solution for a lithium-ion battery and a lithium-ion battery which include the same, and particularly, to a non-aqueous electrolyte solution, which may remove an acid generated by the decomposition of a lithium salt while being able to suppress the dissolution of metal impurities causing failure in the battery by using and including a Lewis base compound containing a propargyl group as a non-aqueous electrolyte solution additive for a lithium-ion battery, and a lithium secondary battery in which transition metal dissolution in a positive electrode and a low-voltage phenomenon are improved.

Abstract: The present invention relates to a non-aqueous electrolyte solution additive, and a non-aqueous electrolyte solution for a lithium secondary battery and a lithium secondary battery which include the same, and particularly, to a non-aqueous electrolyte solution additive including a compound based on a cyclic sulfur structure, and a secondary battery in which low-voltage failure due to metal dissolution may be improved by including the same.

Abstract: A semiconductor memory apparatus includes first and second byte pads. A left-side peri-line couples the first byte pad and a first memory bank region and a right-side peri-line couples the second byte pad and a second memory bank region. A peri-repeater couples the left-side peri-line and the right-side peri-line based on a peri-strobe signal. The peri-strobe signal is generated based on byte information and memory bank selection information.

Abstract: A semiconductor device includes a synthesis control signal generation circuit and a data output control circuit. The synthesis control signal generation circuit generates a synthesis control signal for determining a burst sequence from a latch control signal in response to a first burst mode command and a second burst mode command. The data output control circuit outputs data included in a bank group as internal data in response to the synthesis control signal.

Abstract: A semiconductor device includes a data detection circuit configured to detect a number of bits having a predetermined logic level among bits included in data to generate a detection signal. The semiconductor device also includes a selection/transmission circuit configured to output the detection signal or a control data signal as a pre-masking signal based on a selection/transmission signal. The semiconductor device further includes a masking signal generation circuit configured to latch the pre-masking signal based on a pipe input control signal and configured to output the latched signal of the pre-masking signal as a masking signal for controlling a data masking operation based on a pipe output control signal.

Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.

Abstract: A semiconductor apparatus including a pipe latch is provided. The pipe latch includes a first latch unit, a second latch unit and an output unit. The first latch unit configured to store an input signal into a first latch node based on a first input control signal. The second latch unit configured to store the signal stored in the first latch node into a second latch node based on a second input control signal. The output unit configured to output the signal stored in the second latch node as output signal based on an output control signal.

Abstract: A semiconductor memory device includes a memory region including a plurality of memory blocks, and suitable for outputting first and second read data from first and second memory blocks among the plurality of memory blocks based on first and second read control signals and a read address signal; a scheduler suitable for outputting a read scheduling signal based on the first and second read control signals; and an output driver suitable for outputting the first and second read data by a predetermined burst length alternately twice or more to a data pad based on a mode signal, wherein the first read data are outputted to the data pad according to a first burst sequence, and the second read data are outputted to the data pad according to a second burst sequence, based on the read scheduling signal.

Abstract: A strobe signal generation circuit includes a trigger circuit configured to generate a pull-up signal and a pull-down signal according to a clock signal; a first main driver configured to generate a differential data strobe signal in response to receiving the pull-up signal and the pull-down signal; and a second main driver configured to generate an other differential data strobe signal in response to receiving the pull-up signal and the pull-down signal from among the at least one pull-down signal through opposite terminals than the first main driver received the pull-up signal and the pull-down signal.

Abstract: A semiconductor memory apparatus includes first and second byte pads. A left-side peri-line couples the first byte pad and a first memory bank region and a right-side peri-line couples the second byte pad and a second memory bank region. A peri-repeater couples the left-side peri-line and the right-side peri-line based on a peri-strobe signal. The peri-strobe signal is generated based on byte information and memory bank selection information.

Abstract: A semiconductor memory apparatus may include a data control circuit, an input/output circuit block, and a data line repeater block. The data control circuit may generate a data control flag signal based on an operation control signal and data. The input/output circuit block may perform a data bus inversion operation for the data, based on the data control flag signal. The data line repeater block may perform a data masking operation for the data based on the data control flag signal.

Abstract: A semiconductor system includes a controller operatively coupled to a semiconductor device, the controller being suitable in a training mode for receiving an external signal and a first data signal from an external device and for transmitting the received external signal and the first data signal to the semiconductor device; and the semiconductor device being suitable in the training mode for determining a level of a reference voltage in response to the first data signal, and for transmitting a second data signal to the controller by buffering the external signal based on the reference voltage without performing a termination operation during an output period of the second data signal, wherein the controller controls an enable timing of the external signal by receiving the second data signal.

Abstract: A memory apparatus may include a plurality of ranks commonly coupled to an input/output (I/O) terminal. Non-target ranks other than a target rank among the plurality of ranks may be configured to perform an on die termination operation based on a read operation of the target rank.

Abstract: A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.

Abstract: A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.