Abstract: According to example embodiments, a logic device includes a first functional block configured to perform a first operation according to first operation information and a second operation according to second operation information, and a second functional block configured to perform a third operation according to the first operation information and a fourth operation according to the second operation information. The first functional block is configured to receive configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the first or second operation based on the selected first or second operation information.

Abstract: A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation.

Abstract: A logic device includes first and second logic blocks and a connection block. Each of the first and second logic blocks configured to perform at least one function, the first logic blocks connected to first connection lines and the second logic blocks connected to second connection lines. The connection block electrically connected to the first and second logic blocks via the first connection lines and the second connection lines, respectively. The connection block including connection cells configured to select one of multiple connection configurations between the first connection lines and the second connection lines based on a desired function.

Abstract: Nonvolatile memory apparatuses and methods of operating the same. A nonvolatile memory apparatus includes a nonvolatile memory cell array including a plurality of memory cells; an address decoder configured to receive computation data that indicates a computation from among a plurality of computations and an input data for computation, and the address decoder configured to output an address of the nonvolatile memory cell array corresponding to the indicated computation and input data, the nonvolatile memory cell array being configured to output result data stored at the output address, the result data corresponding to a previous computation performed before receipt of the computation data; and a reading unit configured to read the result data output from the nonvolatile memory cell array.

Abstract: The present invention provides an AGE inhibitor and a health functional food for inhibiting an occurrence of diabetic complications. Particularly, the present invention comprises a compound selected from the group consisting of mulberrofuran G, mulberrofuran K, kuwanon G, kuwanon Z, oxyresveratrol, 2?,4?,5,7-tetrahydroxyflavanone, morusignin L and dihydromorin isolated from Morus Bark as an active ingredient. The compounds disclosed above inhibit the production of AGE which is a causative substance of diabetic complications. Thus, the compounds could be used as an AGE inhibitor and a health functional food for inhibiting diabetic nephropathy, diabetic retinopathy and diabetic neuropathy.

Abstract: The logic circuit includes at least one variable resistance device configured such that a resistance value of the at least one variable resistance device varies according to at least one selected value. The selected value is selected from among a voltage and a current of an input signal, and the at least one variable resistance device is configured to memorize the resistance value. The logic circuit is configured to store multi-level data by setting the memorized resistance value.

Abstract: A high side gate driver, a switching chip, and a power device, which respectively include a protection device, are provided. The high side gate driver includes a first terminal configured to receive a first low level driving power supply that is provided to turn off the high side normally-on switch; a first switching device connected to the first terminal; and a protection device connected in series between the first switching device and a gate of the high side normally-on switch, the protection device configured to absorb a majority of a voltage applied to a gate of the high side normally-on switch. The power device includes the high side gate driver. In addition, the switching chip includes a high side normally-on switch, an additional normally-on switch, and a low side normally-on switch, which have a same structure.

Abstract: A power management chip and a power management device including the power management chip. The power management chip includes at least one power switch and a driver unit for generating a driving signal for driving the at least one power switch, the driver unit including one or more circuit units formed on a same substrate as the at least one power switch.

Abstract: A power module including a power device and a periphery circuit configured to suppress a leakage current in the power device. The periphery circuit includes a leakage current detection circuit configured to detect a leakage current from the power device and control operation of the power device based on a result of the detection. The leakage current detection circuit including an input terminal connected to the power device, a plurality of NMOS transistors, a plurality of PMOS transistors connected to the plurality of NMOS transistors, and a comparator.

Abstract: In one example embodiment, the semiconductor device includes a memory cell array having at least one memory cell disposed in a region at which at least one bit line and at least one word line cross. A sensing unit senses data stored in the at least one memory cell. The sensing unit includes a connection control unit configured to control a connection between the at least one bit line and a sensing line based on a control signal, the control signal having a voltage level that varies based on a value of data being sensed by the sensing unit.

Abstract: Example embodiments provide a reconfigurable logic device including at least two logic blocks having a first logic block and a second logic block, a global wire group including at least a plurality of first global wires connected to the first logic block and a plurality of second global wires connected to the second logic block, and a global controller including a plurality of first nonvolatile memory devices associated with at least one first global wire and one second global wire, the global controller configured to selectively couple the pluralities of first and second global wires based on first data stored in the associated first nonvolatile memory devices.

Abstract: A digital-to-analog converter (DAC) includes: a plurality of first controllers and a plurality of resistor devices. The plurality of first controllers are configured to be selectively switched on according to a received digital signal to control an analog signal according to the received digital signal. The plurality of resistor devices are respectively connected to the plurality of first controllers. The plurality of resistor devices include non-volatile memory devices.

Abstract: Oscillators and methods of operating the oscillators are provided, the oscillators include an oscillating unit including at least one magnetic layer having a magnetization direction that varies according to at least one selected from the group consisting of an applied current, an applied voltage and an applied magnetic field. The oscillating unit is configured to generate an oscillation signal having a set frequency. The oscillators further include an output stage that provides an output signal by differentially amplifying the oscillation signal.

Abstract: A multi-valued logic device having an improved reliability includes a conversion unit configured to convert a multi level signal into a plurality of partial signals; and a plurality of nonvolatile memory devices configured to individually store the plurality of partial signals, wherein a number of bits of each of the plurality of partial signals individually stored in the plurality of nonvolatile memory devices is less than the number of bits of the multi level signal.

Abstract: The present invention relates to a method and apparatus for recognizing a motion pattern formed by a continued contact surface. A method for recognizing a motion patter according to an embodiment of the invention may comprise receiving a motion pattern as input from a user, comparing pattern information of the motion pattern with pattern information of a preset release pattern, and determining a mismatch level of the motion pattern according to the comparison result. According to an embodiment of the invention, if an inputted motion pattern does not match the preset release pattern, the degree of mismatch is determined with different levels, to respond in various ways other than simply maintaining the locked state.

Abstract: A logic device may include a first functional block, the first functional block including, a first storage block, a second storage block, and a first function controller. In a first operation time period, the first function controller may be configured to receive a first configuration selection signal and a first configuration command signal that instructs a first function be configured, select the first storage block as a configured storage block in the first operation time period based on the first configuration selection signal, and configure the first function in the first storage block based on the first configuration command signal.

Abstract: According to example embodiments, a logic device includes a first functional block configured to perform a first operation according to first operation information and a second operation according to second operation information, and a second functional block configured to perform a third operation according to the first operation information and a fourth operation according to the second operation information. The first functional block is configured to receive configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the first or second operation based on the selected first or second operation information.

Abstract: A logic device that includes a plurality of non-volatile memory cells configured to store possible output results related to the input signal. The logic device generating an output signal by selecting and accessing one of the plurality of non-volatile memory cells based on the input signal.

Abstract: The logic circuit includes at least one variable resistance device configured such that a resistance value of the at least one variable resistance device varies according to at least one selected value. The selected value is selected from among a voltage and a current of an input signal, and the at least one variable resistance device is configured to memorize the resistance value. The logic circuit is configured to store multi-level data by setting the memorized resistance value.

Abstract: In one example embodiment, the semiconductor device includes a memory cell array having at least one memory cell disposed in a region at which at least one bit line and at least one word line cross. A sensing unit senses data stored in the at least one memory cell. The sensing unit includes a connection control unit configured to control a connection between the at least one bit line and a sensing line based on a control signal, the control signal having a voltage level that varies based on a value of data being sensed by the sensing unit.