Abstract: A test device for testing a plurality of semiconductor devices, each of which includes a plurality of functional blocks and a plurality of test pads coupled to the functional blocks. The test device includes a test header including a plurality of test channels, a plurality of test sites on which the semiconductor devices are installed, and a test control device. The test control device allocates the test channels to at least some of the test pads of the semiconductor devices to test more than two of the semiconductor devices simultaneously. The number of the test sites is greater than a value generated by dividing the number of the test channels by the number of the test pads of each of the semiconductor devices.

Abstract: A test device for testing a plurality of semiconductor devices, each of which includes a plurality of functional blocks and a plurality of test pads coupled to the functional blocks. The test device includes a test header including a plurality of test channels, a plurality of test sites on which the semiconductor devices are installed, and a test control device. The test control device allocates the test channels to at least some of the test pads of the semiconductor devices to test more than two of the semiconductor devices simultaneously. The number of the test sites is greater than a value generated by dividing the number of the test channels by the number of the test pads of each of the semiconductor devices.