Abstract: A memory device may include an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers that are alternately stacked on a substrate; a trench in the electrode structure, and having an upper sidewall, a lower sidewall and a horizontal portion that couples the upper sidewall to the lower sidewall and that is parallel to a top surface of the substrate; a dielectric layer in the trench; and a slimming hole in the electrode structure having a sidewall of the trench and a region of the dielectric layer, and having a bottom surface disposed on an electrode layer on which the horizontal portion of the trench is positioned.

Abstract: A semiconductor device includes a stack including a plurality of electrode layers which include a plurality of capacitor first electrode layers and a plurality of capacitor second electrode layers alternately stacked on a substrate and a plurality of dielectric layers which are disposed alternately with the plurality of electrode layers; a first conductive pillar passing through the stack and coupled to the plurality of capacitor first electrode layers; a second conductive pillar passing through the stack and coupled to the plurality of capacitor second electrode layers; and a plurality of insulation layer patterns insulating the first conductive pillar and the plurality of capacitor second electrode layers from each other and insulating the second conductive pillar and the plurality of capacitor first electrode layers from each other.

Abstract: A three-dimensional memory device and a manufacturing method thereof. The three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; and a plurality of through holes passing through the electrode structure in a vertical direction, and including pad regions at the transition between portions of the through holes have different widths.

Abstract: A direct water purifier includes a first filter for filtering water introduced through a first flow path; a second filter for receiving the water supplied from the first filter through a second flow path and filtering the same; a first valve disposed in the second flow path to control water flow; a pump disposed in the second flow path to supply water having a predetermined hydraulic pressure or higher to the second filter; a third filter for receiving the water supplied from the second filter through a third flow path and filtering the same; a heating part for receiving the water supplied from the third filter and heating the same to a predetermined temperature; and a flushing valve disposed in a flushing flow path through which concentrated water is discharged from the second filter, wherein the flushing valve is opened during operation of the heating part.

Abstract: A water purifier capable of stably discharging residual water from an extraction unit is disclosed. The water purifier (100) comprises: a filter unit (110) having a reverse osmosis membrane filter (113) for filtering incoming water; an extraction unit (160) for providing purified water filtered by the filter unit (110) to a user; and a residual water drainage unit (150) configured to drain, through the reverse osmosis membrane filter (113), residual water remaining in the extraction unit (160), by using an osmotic phenomenon of the reverse osmosis membrane filter (113) after completion of the extraction through the extraction unit (160).

Abstract: Disclosed is a hot water discharging apparatus. A hot water discharging apparatus according to an embodiment of the present invention comprises: a water heater for heating water that has flowed into hot water, and discharging the hot water; and a hot water discharge unit that is connected to the water heater so that the hot water discharged from the water heater is discharged to the outside, wherein the water heater is provided with an outlet through which the hot water is discharged, the hot water discharge unit includes a hot water discharge member connected to the outside so that the hot water is discharged to the outside, and the water heater may be disposed so that the outlet is located higher than the hot water discharge-side end of the hot water discharge member.

Abstract: Disclosed is a condenser for a water purifier, comprising a pipe provided with a plurality of bending parts which are disposed so as to be vertically overlapping with one another, cooling wires provided on the upper and lower surfaces of the plurality of bending parts; and fixing members for fixing the cooling wires. The cooling wires that are provided on the surfaces, facing each other, of the plurality of bending parts are disposed so as to alternate with each other.

Abstract: An apparatus for fixing an insert member in a mold includes a groove formed on the inner circumferential surface of the insert member, a coupling protrusion protruding from the mold so that the insert member is inserted over the coupling protrusion, at least one hook member coupled to the mold such that a hook member moves between a protrusion position and a retreat position, and a driving unit for moving the at least one hook member between the protrusion position and the retreat position, wherein when the hook member is located at the protrusion position, the one end of the hook member engages with the groove of the insert member, and when the hook member is located at the retreat position, the one end of the hook member disengages from the groove of the insert member.

Abstract: A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction; and a cell region including a plane which is coupled to the plurality of bit lines, wherein the plane is divided into a plurality of memory groups each including a plurality of partial pages to be disposed in a plurality of rows in the first direction.

Abstract: The present disclosure relates to a method of reducing a Peak to Average Power Ratio (PAPR) in a communication device, and more particularly, to a method of Crest Factor Reduction (CFR) processing of a signal in order to reduce a PAPR in a communication device such as a repeater. The communication device includes: a first CFR module configured generate a first processed signal by CFR processing an original signal; and a second CFR module configured generate a second processed signal by CFR processing the first processed signal, wherein the first processed signal is generated using a first sampling rate, and the second processed signal is generated using a second sampling rate. According to the disclosure, even a communication device with a low sampling rate may effectively remove a peak component of an input signal.

Abstract: A direct water purifier includes a first filter for filtering water introduced through a first flow path; a second filter for receiving the water supplied from the first filter through a second flow path and filtering the same; a first valve disposed in the second flow path to control water flow; a pump disposed in the second flow path to supply water having a predetermined hydraulic pressure or higher to the second filter; a third filter for receiving the water supplied from the second filter through a third flow path and filtering the same; a heating part for receiving the water supplied from the third filter and heating the same to a predetermined temperature; and a flushing valve disposed in a flushing flow path through which concentrated water is discharged from the second filter, wherein the flushing valve is opened during operation of the heating part.

Abstract: A direct water purifier includes a first filter for filtering water introduced through a first flow path; a second filter for receiving the water supplied from the first filter through a second flow path and filtering the same; a first valve disposed in the second flow path to control water flow; a pump disposed in the second flow path to supply water having a predetermined hydraulic pressure or higher to the second filter; a third filter for receiving the water supplied from the second filter through a third flow path and filtering the same; a heating part for receiving the water supplied from the third filter and heating the same to a predetermined temperature; and a flushing valve disposed in a flushing flow path through which concentrated water is discharged from the second filter, wherein the flushing valve is opened during operation of the heating part.

Abstract: A method for manufacturing a three-dimensional memory device includes forming a lower multi-layered stack by alternately stacking a plurality of first dielectric layers and a plurality of first sacrificial layers on a substrate; forming an etch stop layer on the lower multi-layered stack; forming an upper multi-layered stack by alternately stacking a plurality of second dielectric layers and a plurality of second sacrificial layers on the etch stop layer; forming a vertical trench by etching the upper multi-layered stack using the etch stop layer as an etch end target; removing the etch stop layer under the vertical trench; and forming a first stairway-shaped trench in the lower multi-layered stack under the vertical trench, and forming a second stairway-shaped trench in the upper multi-layered stack.

Abstract: Disclosed is a water purifier. A water purifier according to one example of the present invention includes: a filter unit including a reverse osmosis filter; a water outlet unit including a water outlet member connected to the filter; and a control unit for discharging water filtered by the filter unit to the outside through the water outlet member, wherein the reverse osmosis filter is provided with a reverse osmosis film that divides the reverse osmosis filter into a non-filtering side and a filtering side, and the control unit causes the filtering side to be flushed before the water filtered by the filter unit is discharged through the water outlet member, and can cause the non-filtering side to be flushed after the water filtered by the filter unit is discharged through the water outlet member.

Abstract: A semiconductor device includes a first semiconductor chip including a memory cell array and a plurality of bit lines; a second semiconductor chip including a peripheral circuit, and bonded to the first semiconductor chip; and a shielding member including a link pattern that is configured in a bonding metal layer of any one of the first semiconductor chip and the second semiconductor chip, and has a grid shape or stripe shapes, and a plurality of island patterns that are configured in a bonding metal layer of the other one of the first semiconductor chip and the second semiconductor chip, and bonded to the link pattern.

Abstract: A three-dimensional semiconductor device includes a peripheral circuit device layer that includes a page buffer area, a pass transistor area adjacent to the page buffer layer, and a logic transistor area adjacent to the pass transistor area in the first direction, and a memory cell device layer that includes a cell area and a staircase area extending from the cell area. The peripheral circuit device layer includes transistors, peripheral circuit via plugs, and peripheral circuit interconnection layers on a substrate. The memory cell device layer includes word line stack including interlayer insulating layers and word lines alternately stacked, the word line stack including end portions stacked in a staircase in the staircase area; a bit line array including bit lines arranged in the cell area; and word line pillars electrically connected to the end portions of the word lines in the staircase area, respectively.

Abstract: A semiconductor device includes a stack including a plurality of electrode layers which include a plurality of capacitor first electrode layers and a plurality of capacitor second electrode layers alternately stacked on a substrate and a plurality of dielectric layers which are disposed alternately with the plurality of electrode layers; a first conductive pillar passing through the stack and coupled to the plurality of capacitor first electrode layers; a second conductive pillar passing through the stack and coupled to the plurality of capacitor second electrode layers; and a plurality of insulation layer patterns insulating the first conductive pillar and the plurality of capacitor second electrode layers from each other and insulating the second conductive pillar and the plurality of capacitor first electrode layers from each other.

Abstract: A memory device may include an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers that are alternately stacked on a substrate; a trench in the electrode structure, and having an upper sidewall, a lower sidewall and a horizontal portion that couples the upper sidewall to the lower sidewall and that is parallel to a top surface of the substrate; a dielectric layer in the trench; and a slimming hole in the electrode structure having a sidewall of the trench and a region of the dielectric layer, and having a bottom surface disposed on an electrode layer on which the horizontal portion of the trench is positioned.

Abstract: A semiconductor memory device includes a first semiconductor layer including a memory cell array; a second semiconductor layer including a first substrate and a page buffer circuit which is configured on the first substrate; a third semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer in a vertical direction, and including a second substrate and a second logic circuit which is configured on an element region of the second substrate; and a first contact plug passing through a coupling region of the second substrate which overlaps the page buffer circuit in the vertical direction.

Abstract: A three-dimensional memory device and a manufacturing method thereof. The three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; and a plurality of through holes passing through the electrode structure in a vertical direction, and including pad regions at the transition between portions of the through holes have different widths.