Abstract: A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity.

Abstract: A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.

Abstract: A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity.

Abstract: A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.

Abstract: A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.

Abstract: A semiconductor device having reduced contact region area achieved at least in part by forming pad portions of the word lines using an asymmetric stair shape separately formed in first and second pad structures. Contact region area is reduced when compared with manufacturing processes known in the art. This leads to an increase in device integrity and a less complex manufacturing process.

Abstract: A semiconductor device having reduced contact region area achieved at least in part by forming pad portions of the word lines using an asymmetric stair shape separately formed in first and second pad structures. Contact region area is reduced when compared with manufacturing processes known in the art. This leads to an increase in device integrity and a less complex manufacturing process.

Abstract: A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.

Abstract: A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity.

Abstract: An embodiment of the invention relates to a method of forming an isolation layer of a flash memory device. An isolation layer is formed using a PSZ-based material and a nitride film of liner form is deposited on a trench before the PSZ film is deposited. An oxide film can be prevented from remaining on a top of the sidewalls of a conductive film for a floating gate through an etch process employing the etch rate. The thickness of a dielectric film can be prevented from increasing when a dielectric film is deposited. Accordingly, the contact area of the floating gate and the dielectric film can be increased and the coupling ratio between the floating gate and the control gate can be improved.

Abstract: A method of fabricating a semiconductor memory device to protect a tunneling insulating layer from etching-damage includes the steps of forming sequentially a tunnel insulating layer, a first conductive layer, a dielectric layer and a second conductive layer on a semiconductor substrate; etching the second conductive layer, the dielectric layer and the first conductive layer to form gate patterns, the first conductive layer remaining on the tunnel insulating layer between the gate patterns to prevent the tunnel insulating layer from being exposed; performing a cleaning process to remove impurities generated in the etching step; performing an ion implanting process to mono-crystallize the first conductive layer remaining on the tunnel insulating layer; and performing an oxidation process to form an oxide layer on top and side walls of the gate patterns and to convert the mono-crystallized first conductive layer into an insulating layer.

Abstract: A method of fabricating a semiconductor memory device to protect a tunneling insulating layer from etching-damage includes the steps of forming sequentially a tunnel insulating layer, a first conductive layer, a dielectric layer and a second conductive layer on a semiconductor substrate; etching the second conductive layer, the dielectric layer and the first conductive layer to form gate patterns, the first conductive layer remaining on the tunnel insulating layer between the gate patterns to prevent the tunnel insulating layer from being exposed; performing a cleaning process to remove impurities generated in the etching step; performing an ion implanting process to mono-crystallize the first conductive layer remaining on the tunnel insulating layer; and performing an oxidation process to form an oxide layer on top and side walls of the gate patterns and to convert the mono-crystallized first conductive layer into an insulating layer.

Abstract: The present invention relates to semiconductor memory device junction and a method of forming the same. The semiconductor memory device junction may include a semiconductor substrate having gate lines formed thereon, and a junction having first and second junction elements formed by implanting impurities of a different mass into the semiconductor substrate between the gate lines. The method of forming a semiconductor memory device junction may include providing a semiconductor substrate having gate lines, forming an auxiliary layer along a surface of the semiconductor substrate including the gate lines, implanting impurities into the semiconductor substrate between gate lines to form a first junction element, and implanting impurities into the semiconductor substrate to form a second junction element, wherein the impurities implanted to form the first junction element and the second junction element have different masses.

Abstract: An embodiment of the invention relates to a method of forming an isolation layer of a flash memory device. An isolation layer is formed using a PSZ-based material and a nitride film of liner form is deposited on a trench before the PSZ film is deposited. An oxide film can be prevented from remaining on a top of the sidewalls of a conductive film for a floating gate through an etch process employing the etch rate. The thickness of a dielectric film can be prevented from increasing when a dielectric film is deposited. Accordingly, the contact area of the floating gate and the dielectric film can be increased and the coupling ratio between the floating gate and the control gate can be improved.