Patents by Inventor Hyun Sook Yoon

Hyun Sook Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9698066
    Abstract: A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: July 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bo-Ra Lee, Jae-Ho Jeong, Nam-Gyu Baek, Hyo-Seok Woo, Hyun-Sook Yoon, Kwang-Yong Lee
  • Publication number: 20170103929
    Abstract: A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.
    Type: Application
    Filed: July 5, 2016
    Publication date: April 13, 2017
    Inventors: Bo-Ra LEE, Jae-Ho JEONG, Nam-Gyu BAEK, Hyo-Seok WOO, Hyun-Sook YOON, Kwang-Yong LEE
  • Patent number: 9449986
    Abstract: A memory device includes a cell region including a channel region extending to be perpendicular to an upper surface of a substrate, a plurality of gate electrode layers stacked on the substrate adjacently to the channel region, a peripheral circuit region including a first active region disposed in the vicinity of the cell region, a second active region having an area larger than an area of the first active region, a plurality of first contacts connected to the first active region, and a plurality of second contacts connected to the second active region. A distance between the plurality of first contacts is less than that between the plurality of second contacts.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Sook Yoon, Jang Gn Yun, Sun Young Kim, Jae Ho Jeong