Abstract: A data receiver device includes a logic unit configured to generate a test pattern signal, receive a test result signal in the test mode, and compare the test pattern signal with the test result signal to perform a test in the test mode. The data receiver further includes a system frequency control circuit configured to multiply a reference clock signal by a multiplication factor received from the logic unit and to output a test clock signal, an output terminal configured to serialize the test pattern signal based on the test clock signal and to output an output signal, and an input terminal configured to recover a data signal and a data clock signal from an input signal based on the output signal, to deserialize the data signal based on the data clock signal, and to output the test result signal to the logic unit.

Abstract: A frequency calibration apparatus and method are provided. A frequency calibration method includes determining a frequency band according to results of frequency comparisons between a synchronized reference signal whose phase is synchronized to a phase of a prescale signal and a divided signal, and performing a Phase Locked Loop (PLL) operation on a reference signal and the divided signal at the determined frequency band to lock the divided signal.

Abstract: A data receiver device includes a logic unit configured to generate a test pattern signal, receive a test result signal in the test mode, and compare the test pattern signal with the test result signal to perform a test in the test mode. The data receiver further includes a system frequency control circuit configured to multiply a reference clock signal by a multiplication factor received from the logic unit and to output a test clock signal, an output terminal configured to serialize the test pattern signal based on the test clock signal and to output an output signal, and an input terminal configured to recover a data signal and a data clock signal from an input signal based on the output signal, to deserialize the data signal based on the data clock signal, and to output the test result signal to the logic unit.

Abstract: A frequency calibration apparatus and method are provided. A frequency calibration method includes determining a frequency band according to results of frequency comparisons between a synchronized reference signal whose phase is synchronized to a phase of a prescale signal and a divided signal, and performing a Phase Locked Loop (PLL) operation on a reference signal and the divided signal at the determined frequency band to lock the divided signal.

Abstract: A receiver includes first switches for applying either differential signals of an oscillator or a data signal of a transmitter to down-converting mixers; a frequency conversion unit for mixing and applying to the down-converting mixers quadrature signals generated from an arbitrary clock signal generator and the oscillator, and having a PPF for changing a phase difference of I/Q signals according to a control voltage externally applied; a phase difference detection part for checking a phase difference between the I/Q signals and generating the control voltage to be applied to the PPF according to the phase difference so as to correct the phase difference; third switches for applying the data signal processed through the down-converting mixers, filters, and amplifiers to A/D converters and applying the I/Q signals having a predetermined frequency to the phase difference detection part; and a control unit for switching the first and third switches.

Abstract: A ring oscillator and a phase error calibration method are provided. The ring oscillator may include a first voltage-current converter for controlling and outputting an amount of tail current Itail according to a magnitude of a first control voltage applied in feedback in a PLL circuit; a second voltage-current converter for controlling and outputting an amount of shift current according to a magnitude of a second control voltage applied from a system phase error detector; and differential amplifiers for controlling, for output signals, a delay time of signals based on the applied tail current amount and a shift time of the signals based on the shift current amount. Thus, a phase relation between in-phase and quadrature-phase signals outputted from the ring oscillator may be controlled.

Abstract: A ring oscillator and a phase error calibration method are provided. The ring oscillator may include a first voltage-current converter for controlling and outputting an amount of tail current Itail according to a magnitude of a first control voltage applied in feedback in a PLL circuit; a second voltage-current converter for controlling and outputting an amount of shift current according to a magnitude of a second control voltage applied from a system phase error detector; and differential amplifiers for controlling, for output signals, a delay time of signals based on the applied tail current amount and a shift time of the signals based on the shift current amount. Thus, a phase relation between in-phase and quadrature-phase signals outputted from the ring oscillator may be controlled.

Abstract: A receiver includes first switches for applying either differential signals of an oscillator or a data signal of a transmitter to down-converting mixers; a frequency conversion unit for mixing and applying to the down-converting mixers quadrature signals generated from an arbitrary clock signal generator and the oscillator, and having a PPF for changing a phase difference of I/Q signals according to a control voltage externally applied; a phase difference detection part for checking a phase difference between the I/Q signals and generating the control voltage to be applied to the PPF according to the phase difference so as to correct the phase difference; third switches for applying the data signal processed through the down-converting mixers, filters, and amplifiers to A/D converters and applying the I/Q signals having a predetermined frequency to the phase difference detection part; and a control unit for switching the first and third switches.