Abstract: A semiconductor device includes a usable address storage unit for selectively storing addresses of a plurality of memory sets using read data of the plurality of memory sets outputted from a nonvolatile memory during a boot-up operation; a register unit for storing the read data of the plurality of memory sets outputted from the nonvolatile memory during the boot-up operation; and an internal circuit for operating by using the read data of the plurality of memory sets stored in the register unit. Addresses corresponding to usable memory sets excluding already-used memory sets and defective memory sets among the memory sets of the nonvolatile memory are extracted and stored, and thus, although an address is not separately inputted when the nonvolatile memory is programmed, data may be programmed in a programmable (usable) memory set.

Abstract: A semiconductor device includes a boot-up signal generator suitable for generating a boot-up signal based on an external reset signal and a specific mode signal; and an internal circuit suitable for performing a boot-up operation based on the boot-up signal.

Abstract: Provided herein is a semiconductor device including first and second regulators suitable for respectively generating first and second regulating voltages; first and second planes; a first peripheral circuit suitable for operating the first plane using the first regulating voltage; and a second peripheral circuit suitable for operating the second plane using the second regulating voltage, wherein the first regulator further provides a first reference voltage to the second regulator, and wherein the second regulator generates the second regulating voltage based on the first reference voltage.

Abstract: A nonvolatile memory includes a plurality of memory sets, wherein each of the memory sets includes a fir memory cell suitable for storing validity signal indicating data validity of the corresponding memory set, and second memory cells suitable for storing multi-bit data or one or more-bit defect information.

Abstract: A nonvolatile memory includes a plurality of memory sets, wherein each of the memory sets includes a first memory cell suitable for storing a validity signal indicating data validity of the corresponding memory set, and second memory cells suitable for storing multi-bit data or one or more-bit defect information.

Abstract: A semiconductor device includes a boot-up signal generator suitable for generating a boot-up signal based on an external reset signal and a specific mode signal; and an internal circuit suitable for performing a boot-up operation based on the boot-up signals

Abstract: A fuse array circuit includes a power generation block suitable for generating a driving power to be level-shifted at least once in a read operation period, a word line driving block suitable for driving a word line by using the driving power, and a fuse array suitable for outputting information programmed in a fuse that is activated by the driven word line through a bit line.

Abstract: A one-time programmable memory includes a first cell array including a plurality of one-time programmable memory cells, and a second cell array including a plurality of one-time programmable memory cells, wherein the first cell array and the second cell array are programmed separately during a program operation, and read in combination during a read operation.

Abstract: A one-time programmable memory includes a first cell array including a plurality of one-time programmable memory cells, and a second cell array including a plurality of one-time programmable memory cells, wherein the first cell array and the second cell array are programmed separately during a program operation, and read in combination during a read operation.

Abstract: Provided is a semiconductor system and method for repairing the same that may improve repair capacity of the semiconductor system. The semiconductor system comprises a semiconductor circuit configured to output a remaining repair information and perform a repair operation in response to an external command, and a host configured to determine a number of available repairs based on the remaining repair information and provide the semiconductor circuit with the external command based on the number of available repairs.

Abstract: A communication terminal and a driving method thereof are provided. The driving method of a communication terminal includes: forming a transmitting path and an absorption path by controlling a time division duplex (TDD) switch in a transmitting mode to isolate the transmitting path and the receiving path from an absorption path, the transmitting path transmitting a transmitting signal in a wireless scheme, and the absorption path diverged from the transmitting path through a circulator of the TDD switch to block a reflecting signal in the transmitting signal reversely transferred to the transmitting path; processing the transmitting signal through the transmitting path. Because a TDD switch has an isolation function, insertion loss in a transmitting path may be suppressed.

Abstract: Provided is a semiconductor system and method for repairing the same that may improve repair capacity of the semiconductor system. The semiconductor system comprises a semiconductor circuit configured to output a remaining repair information and perform a repair operation in response to an external command, and a host configured to determine a number of available repairs based on the remaining repair information and provide the semiconductor circuit with the external command based on the number of available repairs.

Abstract: A pipe register circuit includes an address storage section configured to temporarily and sequentially store address signals input from an external in correspondence with a read command signal input together with the address signals, and an address output control section configured to generate an address output control signal for allowing the address signals stored in the address storage section to be output in correspondence with CAS latency, and output the address output control signal to the address storage section.

Abstract: A nonvolatile memory includes a plurality of memory sets, wherein each of the memory sets includes a first memory cell suitable for storing a validity signal indicating data validity of the corresponding memory set, and second memory cells suitable for storing multi-bit data or one or more-bit defect information.

Abstract: An operating method of a memory device includes entering a repair mode, receiving an active command and a fail address, and temporarily storing the received command and address, receiving a write command, and determining whether to perform a program operation, when the program operation is determined to be performed, programming the temporarily-stored fail address into a programmable storage unit, and receiving a precharge command before the programming of the temporarily-stored fail address is completed.

Abstract: An operating method of a memory device includes entering a repair mode, receiving an active command and a fail address, and temporarily storing the received command and address, receiving a write command, and determining whether to perform a program operation, when the program operation is determined to be performed, programming the temporarily-stored fail address into a programmable storage unit, and receiving a precharge command before the programming of the temporarily-stored fail address is completed.

Abstract: A one-time programmable memory device may include a normal cell array including a plurality of one-time programmable memory cells, which are programmable and accessible in the normal operation, a test cell array including one-time programmable memory cells, which are programmed at a given pattern in a test operation for determining a failed row and/or a failed column and are not accessible in the normal operation, a row circuit configured to control an operation of a row that is selected by a row address in the normal cell array, and a column circuit configured to access a column that is selected by a column address in the normal cell array.

Abstract: An apparatus and a method for protecting receive circuits in a Time Division Duplexing (TDD) wireless communication system are provided. The receive circuit protecting apparatus includes a TDD controller for controlling transmission and reception modes according to transmission and reception intervals, a transmitter for power-amplifying and outputting a Radio Frequency (RF) signal in the transmission mode under control of the TDD controller, and a Transmit/Receive Antenna Switch (TRAS) for, in the transmission mode, forwarding a signal of the transmitter to an antenna feed line under the control of the TDD controller and for absorbing an output signal of the transmitter flowing to the receive circuits using a reflection structure positioned in a reception path, and, in the reception mode, for forwarding a signal fed from the antenna feed line to the receive circuits under the control of the TDD controller.

Abstract: A pipe register circuit includes an address storage section configured to temporarily and sequentially store address signals input from an external in correspondence with a read command signal input together with the address signals, and an address output control section configured to generate an address output control signal for allowing the address signals stored in the address storage section to be output in correspondence with CAS latency, and output the address output control signal to the address storage section.

Abstract: A semiconductor apparatus includes: odd and even sub word line driving units configured to selectively drive odd sub word lines and even sub word lines among a plurality of sub word lines; a bit line sense amplifier including a plurality of sense amplifier driving lines which are electrically connected with bit lines; a first sense amplifier driving unit formed on one side of the bit line sense amplifier which extends in the same direction as the bit lines, and configured to drive odd sense amplifier driving lines among the plurality of sense amplifier driving lines; and a second sense amplifier driving unit formed on another side of the bit line sense amplifier which extends in the same direction as the bit lines, and configured to drive even sense amplifier driving lines among the plurality of sense amplifier driving lines according to driving of the even sub word lines.