Abstract: The present disclosure relates to a joint surface safety evaluation apparatus and, more particularly, to a joint surface safety evaluation apparatus for generating mesh data consisting of a combination of a plurality of polygonal mesh surfaces, based on stereo image data generated by photographing an evaluation target surface, generating modeling data by overlapping the stereo image data and the mesh data, extracting a mesh surface corresponding to a rock slope surface by applying the modeling data to a learning model, and calculating a joint surface evaluation score regarding the evaluation target surface, by using a normal vector for each of a plurality of extracted mesh surfaces.

Abstract: The present disclosure relates to a joint surface safety evaluation apparatus and, more particularly, to a joint surface safety evaluation apparatus for generating mesh data consisting of a combination of a plurality of polygonal mesh surfaces, based on stereo image data generated by photographing an evaluation target surface, generating modeling data by overlapping the stereo image data and the mesh data, extracting a mesh surface corresponding to a rock slope surface by applying the modeling data to a learning model, and calculating a joint surface evaluation score regarding the evaluation target surface, by using a normal vector for each of a plurality of extracted mesh surfaces.

Abstract: Disclosed is a method of manufacturing a semiconductor device, in which a high-temperature SOD (spin on dielectric) annealing process is performed to prevent a SOD crack, and a nitride film, serving as a capping layer, is formed over the entire surface of a bit line pattern to prevent a tungsten layer, which is a bit line electrode layer, from being oxidized during the high-temperature annealing process. In a process of forming the bit line pattern, over etching is performed to recess a lower interlayer insulating film such that the thickness of the interlayer insulating film to be etched in a subsequent process, that is, a process of etching a storage node contact hole, is reduced. In this way, it is possible to prevent the storage node contact hole from not being opened.

Abstract: Disclosed is a method of manufacturing a semiconductor device, in which a high-temperature SOD (spin on dielectric) annealing process is performed to prevent a SOD crack, and a nitride film, serving as a capping layer, is formed over the entire surface of a bit line pattern to prevent a tungsten layer, which is a bit line electrode layer, from being oxidized during the high-temperature annealing process. In a process of forming the bit line pattern, over etching is performed to recess a lower interlayer insulating film such that the thickness of the interlayer insulating film to be etched in a subsequent process, that is, a process of etching a storage node contact hole, is reduced. In this way, it is possible to prevent the storage node contact hole from not being opened.

Abstract: A plasma etching apparatus includes a plasma processing chamber, an electro static chuck installed in the plasma processing chamber and providing a region where a wafer is to be placed, and a focus ring surrounding an edge of the wafer at an edge portion of the electro static chuck and including: a first region surrounding the edge of the wafer; and a second region disposed under a bottom surface of the wafer. The first region has a surface disposed higher than that of the wafer.