Abstract: Disclosed is a bio illuminance measuring apparatus including a circadian lambda filter passing external light along according to a circadian rhythm sensitivity curve, a visual lambda filter passing the external light along according to a visual sensitivity curve, a photo sensing portion sensing and converting the external light, which has passed through the circadian lambda filter, into a circadian wavelength signal and sensing and converting the external light, which has passed through the visual lambda filter, into a visual wavelength signal, and an illuminance calculating portion which calculates a ratio between the circadian wavelength signal and the visual wavelength signal, calculates a circadian action factor by applying the ratio between the circadian wavelength signal and the visual wavelength signal to a circadian action function which varies according to the visual wavelength signal, and calculates a bio illuminance value of the external light on the basis of the circadian action factor.

Abstract: Disclosed are an apparatus and a system for managing circadian rhythm. The apparatus includes an illuminance measuring portion which measures a bio illuminance value of external light using a circadian lambda filter which passes the external light along according to a circadian rhythm sensitivity curve and a visual lambda filter which passes the external light along according to a visual sensitivity curve, a controller which outputs a control signal for reinforcing a user's circadian rhythm on the basis of the bio illuminance value, and a circadian rhythm reinforcing portion which emits light of a circadian wavelength band toward the user according to the control signal.

Abstract: Disclosed are an apparatus and a system for managing circadian rhythm. The apparatus includes an illuminance measuring portion which measures a bio illuminance value of external light using a circadian lambda filter which passes the external light along according to a circadian rhythm sensitivity curve and a visual lambda filter which passes the external light along according to a visual sensitivity curve, a controller which outputs a control signal for reinforcing a user's circadian rhythm on the basis of the bio illuminance value, and a circadian rhythm reinforcing portion which emits light of a circadian wavelength band toward the user according to the control signal.

Abstract: Disclosed is a bio illuminance measuring apparatus including a circadian lambda filter passing external light along according to a circadian rhythm sensitivity curve, a visual lambda filter passing the external light along according to a visual sensitivity curve, a photo sensing portion sensing and converting the external light, which has passed through the circadian lambda filter, into a circadian wavelength signal and sensing and converting the external light, which has passed through the visual lambda filter, into a visual wavelength signal, and an illuminance calculating portion which calculates a ratio between the circadian wavelength signal and the visual wavelength signal, calculates a circadian action factor by applying the ratio between the circadian wavelength signal and the visual wavelength signal to a circadian action function which varies according to the visual wavelength signal, and calculates a bio illuminance value of the external light on the basis of the circadian action factor.

Abstract: Methods of programming a multi-bit non-volatile memory device are provided. The multi-bit non-volatile memory device includes a memory cell array including a plurality of memory cells and a storage unit electrically coupled to the memory cell array. A first bit (FB) of multi-bit data is programmed from the storage unit into one of the plurality of memory cells in the memory cell array. A second bit (SB) of multi-bit data is programmed from the storage unit into one of the plurality of memory cells in the memory cell array using data inversion. Related memory devices are also provided.

Abstract: A nonvolatile semiconductor memory device comprises a memory array of 3-level nonvolatile memory cells. The memory array comprises first even and odd strings of memory cells connected to respective first even and odd bit lines and second even and odd strings of memory cells connected to respective second even and odd bit lines. The first even and odd bit lines are selectively connected to a first common bit line during data programming and read operations, and the second even and odd bit lines are selectively connected to a second common bit line during data programming and read operations. The device programs and reads data in a pair of memory cells using three bits of data corresponding to three threshold voltage distributions of the 3-level nonvolatile memory cells.

Abstract: Disclosed is a semiconductor memory device including pluralities of memory blocks each of which is segmented into main and spare regions, and a block information storing region storing block information of the memory blocks.

Abstract: Methods of programming a multi-bit non-volatile memory device are provided. The multi-bit non-volatile memory device includes a memory cell array including a plurality of memory cells and a storage unit electrically coupled to the memory cell array. A first bit (FB) of multi-bit data is programmed from the storage unit into one of the plurality of memory cells in the memory cell array. A second bit (SB) of multi-bit data is programmed from the storage unit into one of the plurality of memory cells in the memory cell array using data inversion. Related memory devices are also provided.

Abstract: A nonvolatile semiconductor memory device comprises a memory array of 3-level nonvolatile memory cells. The memory array comprises first even and odd strings of memory cells connected to respective first even and odd bit lines and second even and odd strings of memory cells connected to respective second even and odd bit lines. The first even and odd bit lines are selectively connected to a first common bit line during data programming and read operations, and the second even and odd bit lines are selectively connected to a second common bit line during data programming and read operations. The device programs and reads data in a pair of memory cells using three bits of data corresponding to three threshold voltage distributions of the 3-level nonvolatile memory cells.

Abstract: There is provided an internal voltage generating circuit that reliably supplies a constant internal voltage to the interior of a semiconductor device without regard to an external voltage, where the internal voltage generating circuit compares a first reference voltage with a first internal voltage fed back to generate the first internal voltage following the first reference voltage, receives the first internal voltage to generate a second reference voltage which is more insensitive to fluctuation of the external voltage than the first reference voltage, and compares the second reference voltage with a second internal voltage fed back to generate the second internal voltage which follows the second reference voltage and has a variation gradient smaller than that of the first internal voltage when the external voltage is changed, thereby supplying the second internal voltage to a circuit requiring stabilized internal voltage, which is obtained to increase stability and durability of the operation of the semico

Abstract: There is provided an internal voltage generating circuit that reliably supplies a constant internal voltage to the interior of a semiconductor device without regard to an external voltage, where the internal voltage generating circuit compares a first reference voltage with a first internal voltage fed back to generate the first internal voltage following the first reference voltage, receives the first internal voltage to generate a second reference voltage which is more insensitive to fluctuation of the external voltage than the first reference voltage, and compares the second reference voltage with a second internal voltage fed back to generate the second internal voltage which follows the second reference voltage and has a variation gradient smaller than that of the first internal voltage when the external voltage is changed, thereby supplying the second internal voltage to a circuit requiring stabilized internal voltage, which is obtained to increase stability and durability of the operation of the semico

Abstract: A semiconductor memory device having memory cells connected with pairs of bit lines and word lines comprises a pre-charging part for pre-charging a pair of bit lines in response to a first state control signal at a stand-by mode of the semiconductor memory device; a bit line charging control part for generating a second state control signal to the pre-charging part when a stand-by current failure occurs due to defect in the pair of bit lines, wherein the second state control signal is independent of a pre-charge relating signal externally applied and the pre-charging part cuts-off a supply voltage from being applied to the pair of bit lines with defect; and a bit line floating prevent part for compensatively fixing potential values of the pair of bit lines with defect so that a cell supply voltage is prevented from being applied to the pair of bit lines with defect at a memory access mode of the semiconductor memory device, so that a hard type defect like a stand-by current failure can be repaired regardless

Abstract: A static random access memory (SRAM) device comprises an array of memory cells, a plurality of bit line precharge circuit for selectively delivering current to bit lines in response to a pair of control signals, during normal and burn-in test modes, and a burn-in current source circuit for selectively delivering current to the memory cells selected by the word lines along with the precharge circuit, in response to the control signals, during the burn-in test mode. In burn-in write operation, memory cells can be supplied with enough cell current without large increasing of chip size and power consumption in normal operation mode.