Abstract: Proposed is a non-electric water purifier in which a flow path provided between a water-purifying filter and a water outlet cock is replaced in order to minimize contamination of purified drinking water. The non-electric water purifier includes a main body having a door formed on one side thereof so as to open and close the main body and having and having a receiving space part defined therein, a connector which is coupled replaceably and rotatably to one side of the main body and incudes a raw water passage connected to a raw water inlet and a purified water passage through which purified water flows, at least one filter housing being received in the receiving space part, with a discharge outlet of the filter housing being coupled detachably to the connector, and the water outlet cock which is connected to a discharge opening of the connector and discharges purified water.

Abstract: Disclosed is a side stream flow-type reverse osmosis membrane filter with an increased purified water recovery rate. The filter comprises: a filter housing with a raw water port, a purified water port, and a concentrated water port; an RO filter to purify raw water, thereby sending purified water to an inside thereof and discharging concentrated water, which is filtered out; a central tube for collecting the purified water; a raw water pipe arranged in the central tube and provided with a raw water flow channel in a center portion thereof, with a purified water flow channel formed between the raw water pipe and the central tube; and a raw water distributor for supplying supply a portion of raw water to the upper end of the RO filter and a portion of the raw water the lower end of the RO filter and supplying the purified water to the purified water port.

Abstract: An integer transforming device for a moving-picture compression encoder, associated with the H.264 standard, comprising: a first adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for input data, generating data extended by a predetermined bit number; a second adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for a shifted result of output data of the first adding/subtracting stage, generating data extended by a predetermined bit number; a third adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for an operation result of the second adding/subtracting stage, generating data extended by a predetermined bit number; and a fourth adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for a shifted result of the third adding/subtracting stage, generating data extended by a predetermined bit number.