Abstract: A method for measuring critical dimensions of a pattern using an overlay measuring apparatus is provided. The method includes setting a first scan range, inputting a step pitch for the overlay measuring apparatus, inputting X and Y coordinates of a point on a reticle, and inputting a size of the reference pattern. The method further includes inputting a position of the reference pattern, inputting a second scan range, measuring the size of the reference pattern, and inputting an ideal pattern size. The method still further includes measuring a size and a first Z-axial focus position of a top region of the reference pattern, storing the first Z-axial focus position, measuring a size of the selected pattern of the first wafer using stored reference information, and determining whether the size of the selected pattern is suitable relative to the ideal pattern size.

Abstract: Provided are an overlay mark of a semiconductor device and a semiconductor device including the overlay mark. The overlay mark includes: reference marks formed in rectangular shapes comprising sides in which fine patterns are formed; and comparison marks formed as rectangular shapes which are smaller than the rectangular shapes of the reference marks and formed of fine patterns, wherein the number of comparison marks is equal to the number of reference marks, wherein the reference marks and the comparison marks are formed on different thin films formed on a semiconductor substrate to be used to inspect alignment states of the different thin films, and the overlay mark reflects an effect of aberration of patterns of memory cells through the fine patterns during a calculation of MR (mis-registration).

Abstract: A method for measuring critical dimensions of a pattern using an overlay measuring apparatus is provided. The method includes setting a first scan range, inputting a step pitch for the overlay measuring apparatus, inputting X and Y coordinates of a point on a reticle, and inputting a size of the reference pattern. The method further includes inputting a position of the reference pattern, inputting a second scan range, measuring the size of the reference pattern, and inputting an ideal pattern size. The method still further includes measuring a size and a first Z-axial focus position of a top region of the reference pattern, storing the first Z-axial focus position, measuring a size of the selected pattern of the first wafer using stored reference information, and determining whether the size of the selected pattern is suitable relative to the ideal pattern size.

Abstract: A method for obtaining an image using a selective combination of wavelengths of light includes dispersing a light in accordance with wavelength bands of the light using a dispersing member, irradiating the dispersed light onto an object to measure reflectivities of the light reflected from the object in accordance with the wavelength bands of the light, comparing reflectivity differences between an objective region and a peripheral region of the object, selecting wavelength bands having the reflectivity differences indicated as either positive values or negative values, adjusting the dispersing member to transmit only the light having the selected wavelength bands, passing light only having the selected wavelength bands through the dispersing member to irradiate the light that has passed through the dispersing member onto the object, taking photographs of the object using the irradiated light, and superposing the photographs of the object to obtain the image of the object.

Abstract: A semiconductor wafer overlay correction method for an exposure process in a semiconductor fabricating stepper incorporates variations in equipment characteristics with time. The wafer overlay correction method includes measuring an overlay error correction value of a semiconductor wafer that is exposed by the stepper, calculating an overlay error correction value by summing the measured overlay error correction value, a variation in the stepper characteristics that is obtained through an empirical characterization of input changes, and a weighting value obtained from a predetermined plurality of wafer lots, and providing the calculated overlay error correction value to the semiconductor fabricating stepper to control an exposure process of a subsequent wafer lot.

Abstract: A method for obtaining an image using a selective combination of wavelengths of light includes dispersing a light in accordance with wavelength bands of the light using a dispersing member, irradiating the dispersed light onto an object to measure reflectivities of the light reflected from the object in accordance with the wavelength bands of the light, comparing reflectivity differences between an objective region and a peripheral region of the object, selecting wavelength bands having the reflectivity differences indicated as either positive values or negative values, adjusting the dispersing member to transmit only the light having the selected wavelength bands, passing light only having the selected wavelength bands through the dispersing member to irradiate the light that has passed through the dispersing member onto the object, taking photographs of the object using the irradiated light, and superposing the photographs of the object to obtain the image of the object.

Abstract: A semiconductor wafer overlay correction method for an exposure process in a semiconductor fabricating stepper incorporates variations in equipment characteristics with time. The wafer overlay correction method includes measuring an overlay error correction value of a semiconductor wafer that is exposed by the stepper, calculating an overlay error correction value by summing the measured overlay error correction value, a variation in the stepper characteristics that is obtained through an empirical characterization of input changes, and a weighting value obtained from a predetermined plurality of wafer lots, and providing the calculated overlay error correction value to the semiconductor fabricating stepper to control an exposure process of a subsequent wafer lot.