Patents by Inventor Hyun Uk Kim

Hyun Uk Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140087939
    Abstract: A metal-carbon composite supported catalyst for hydrogen production using co-evaporation and a method of preparing the same, wherein the catalyst is configured such that a metal-carbon composite having a core-shell structure resulting from co-evaporation is supported on the surface of an oxide-based support coated with carbon, thereby maintaining superior durability without agglomeration even in a catalytic reaction at a high temperature. Because part or all of the surface of metal is covered with the carbon shell, even when the catalyst is applied under severe reaction conditions including high temperatures, long periods of time, acidic or alkaline states, etc., the metal particles do not agglomerate or are not detached, and do not corrode, thus exhibiting high performance and high durability. Therefore, inactivation of the catalyst or the generation of side reactions can be prevented, so that the catalyst can be efficiently utilized in hydrogen production.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 27, 2014
    Inventors: Hee Yeon Kim, Seok Yong Hong, Hyun Uk Kim
  • Patent number: 8169064
    Abstract: A package on package system is provided including providing a first substrate having a first integrated circuit thereon and a second substrate having a second integrated circuit thereon, the second substrate having a recess provided therein. The first and second substrates are mounted having the first integrated circuit at least partially nested in the recess.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: May 1, 2012
    Assignees: Stats Chippac Ltd., Stats Chippac, Inc.
    Inventor: Hyun Uk Kim
  • Patent number: 7674640
    Abstract: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top package by the top substrate over the bottom substrate and electrically connecting the bottom and top substrates. Mounting system electrical connectors under the bottom substrate adjacent the bottom die.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: March 9, 2010
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jong-Woo Ha, Myung Kil Lee, Hyun Uk Kim, Taebok Jung
  • Publication number: 20070290319
    Abstract: A package on package system is provided including providing a first substrate having a first integrated circuit thereon and a second substrate having a second integrated circuit thereon, the second substrate having a recess provided therein. The first and second substrates are mounted having the first integrated circuit at least partially nested in the recess.
    Type: Application
    Filed: August 31, 2007
    Publication date: December 20, 2007
    Inventor: Hyun Uk Kim
  • Patent number: 7279785
    Abstract: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top package by the top substrate over the bottom substrate and electrically connecting the bottom and top substrates. Mounting system electrical connectors under the bottom substrate adjacent the bottom die.
    Type: Grant
    Filed: November 12, 2005
    Date of Patent: October 9, 2007
    Assignee: Stats Chippac Ltd.
    Inventors: Jong-Woo Ha, Myung Kil Lee, Hyun Uk Kim, Taebok Jung
  • Patent number: 7279786
    Abstract: A package on package system is provided including providing a first substrate having a first integrated circuit thereon and a second substrate having a second integrated circuit thereon, the second substrate having a recess provided therein. The first and second substrates are mounted having the first integrated circuit at least partially nested in the recess.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: October 9, 2007
    Assignees: Stats Chippac Ltd., Stats Chippac, Inc.
    Inventor: Hyun Uk Kim
  • Publication number: 20060180914
    Abstract: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top package by the top substrate over the bottom substrate and electrically connecting the bottom and top substrates. Mounting system electrical connectors under the bottom substrate adjacent the bottom die.
    Type: Application
    Filed: November 12, 2005
    Publication date: August 17, 2006
    Applicant: STATS CHIPPAC LTD.
    Inventors: Jong-Woo Ha, Myung Kil Lee, Hyun Uk Kim, Taebok Jung