Abstract: An overlay measurement device includes a transmission and receipt part and a processor connecting to the transmission and receipt part electrically. The processor obtains data transmitted from a user terminal through the transmission and receipt part, analyzes a recipe included in the data, and performs optimization of measurement options of a wafer, based on the recipe, after the recipe is analyzed.

Abstract: An overlay measurement device for measuring an error between a first overlay mark and a second overlay mark respectively formed on different layers of a wafer, includes: a light source; an aperture that changes a beam from the light source to be suitable for photographing the first overlay mark or the second overlay mark; a detector for obtaining an image of the first overlay mark or an image of the second overlay mark; a transmission and receipt part; and a processor connecting to the transmission and receipt part electrically.

Abstract: An overlay measurement device for measuring an error between a first overlay mark and a second overlay mark respectively formed on different layers of a wafer, includes: a light source; an objective lens that concentrates a beam from the light source on a measurement position of the wafer, and gathers the beam being reflected in the measurement positon; a lens focus actuator that adjusts a distance between the objective lens and the wafer such that a focus surface is placed at the first overlay mark or the second overlay mark; an auto focus module that adjusts a focus by adjusting the lens focus actuator; a detector for obtaining an image of the first overlay mark or an image of the second overlay mark; a transmission and receipt part; and a processor connecting to the transmission and receipt part electrically.

Abstract: A non-transitory computer-readable storage medium that records a data structure for storing data controlling an operation of an overlay measurement device that measures an error between a first overlay mark and a second overlay mark formed on different layers of a wafer. The data include information of a recipe that is input to allow the overlay measurement device to measure characteristics of a wafer through a manager program installed in a user terminal, and unique information of the overlay measurement device.

Abstract: A non-transitory computer-readable storage medium that records a data computer-readable storage medium that records a data structure for storing data controlling an operation of an overlay measurement device that measures an error between a first overlay mark and a second overlay mark formed on different layers of a wafer. The data include information of a recipe that is input to allow the overlay measurement device to measure characteristics of a wafer through a manager program installed in a user terminal, and unique information of the overlay measurement device.

Abstract: A non-transitory computer-readable storage medium that records a data structure for storing data controlling an operation of an overlay measurement device that measures an error between a first overlay mark and a second overlay mark formed on different layers of a wafer. The data include: information of a recipe that is input to allow the overlay measurement device to measure characteristics of a wafer through a manager program installed in a user terminal, and unique information of the overlay measurement device. The overlay measurement device includes: a light source, an aperture that changes a beam from the light source to be suitable for photographing the first overlay mark or the second overlay mark, a detector that acquires an image of the first overlay mark and an image of the second overlay mark, a transceiver, and a processor electrically connected to the transceiver.

Abstract: An overlay measurement device for measuring an error between a first overlay mark and a second overlay mark respectively formed on different layers of a wafer, includes: a light source; an aperture that changes a beam from the light source to be suitable for photographing the first overlay mark or the second overlay mark; a detector for obtaining an image of the first overlay mark or an image of the second overlay mark; a transmission and receipt part; and a processor connecting to the transmission and receipt part electrically.

Abstract: A display device includes: a display panel; an emission driver; a scan driver; and a timing controller. The display panel includes light emitting pixels and photosensitive pixels, where the photosensitive pixels are operated in an initialization period, a light exposure period and a sensing period. The emission driver supplies emission control signals to emission control lines connected to the light emitting pixels, based on an emission start signal. The scan driver supplies scan signals to scan lines connected to the light emitting pixels and the photosensitive pixels, based on a scan start signal. The timing controller generates the emission start signal having a single pulse of a gate-off level and the scan start signal having a single pulse of a gate-on level in a last frame period among frame periods corresponding to the light exposure period and in each of frame periods corresponding to the sensing period.

Abstract: A display apparatus including a display and a supporter. The supporter being mounted on the display and configured to support the display and rotate the display module between a first position and a second position. The supporter including a drive motor, a first gear, and a detection sensor. The drive motor configured to supply a driving force to rotate the display. The first gear configured to rotate together with the display by receiving the driving force from the drive motor. The detection sensor configured to detect a rotation amount of a second gear configured to rotate in with the first gear.

Abstract: A display device comprises a display panel comprising an image display area and a non-display area, display pixels comprising light-emitting elements in the image display area and pixel driving units connected to the light-emitting elements, light-sensing pixels comprising photo-detecting units in a fingerprint sensing area in the image display area, and sense driving units connected to the photo-detecting units, a light-sensing reset driver configured to supply reset signals to the sense driving units of the light-sensing pixels for at least each horizontal line among the light-sensing pixels in response to a line select signal from a display driving circuit; and a fingerprint scan driver configured to sequentially supply a fingerprint scan signal to the sense driving units of the light-sensing pixels in response to a fingerprint scan control signal from the display driving circuit.

Abstract: An overlay measurement device includes a transmission and receipt part and a processor connecting to the transmission and receipt part electrically. The processor obtains data transmitted from a user terminal through the transmission and receipt part, analyzes a recipe included in the data, and performs optimization of measurement options of a wafer, based on the recipe, after the recipe is analyzed.

Abstract: There are provided a computer-readable storage medium and an overlay measurement device therefor that records a data structure for storing data controlling an operation of an overlay measurement device. In a computer-readable storage medium that records a data structure for storing data controlling an operation of an overlay measurement device in one embodiment, the data includes information of a recipe that is input to allow the overlay measurement device to measure characteristics of a wafer through a manager program installed in a user terminal, and unique information of the overlay measurement device.

Abstract: A display apparatus including a display and a supporter. The supporter being mounted on the display and configured to support the display and rotate the display module between a first position and a second position. The supporter including a drive motor, a first gear, and a detection sensor. The drive motor configured to supply a driving force to rotate the display. The first gear configured to rotate together with the display by receiving the driving force from the drive motor. The detection sensor configured to detect a rotation amount of a second gear configured to rotate in with the first gear.

Abstract: A semiconductor circuit may include a first flip-flop configured to output a first input data as a first output signal in response to an inverted input clock signal, a second flip-flop configured to output a second input data as a second output signal in response to an input clock signal, a glitch-free circuit configured to receive the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and to determine a voltage level of a node on the basis of the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and an inverter configured to output an output clock signal obtained by inverting the voltage level of the node determined by the glitch-free circuit. The glitch-free circuit does not include a transistor having a gate connected to the node.

Abstract: A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.

Abstract: A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.

Abstract: A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit.

Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.

Abstract: A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.