Abstract: Provided is a display apparatus. The display apparatus includes an active area and a bezel area, the display apparatus comprising semiconductor patterns disposed in a third area of the bezel area, an insulating layer disposed on the semiconductor patterns and includes contact holes and dummy holes, a power supply electrode disposed in the third area of the bezel area, overlaps the semiconductor patterns with the insulating layer therebetween, and is connected to the semiconductor patterns through the contact holes, dummy gate lines disposed between the semiconductor patterns and the power supply electrode, overlap the semiconductor pattern to form a first compensation capacitance and overlap the power supply electrode to form a second compensation capacitance, and a dummy semiconductor patterns disposed in the third area of the bezel area, and are connected to the power supply electrode through the dummy holes.

Abstract: A display device is disclosed, which may prevent an inorganic film formed in an organic film open area from being damaged and prevent a cathode electrode from being shorted. The display device includes a substrate including a display area on which pixels area arranged, and a non-display area surrounding the display area; a first metal layer formed in the non-display area of the substrate; at least one insulating film arranged on the first metal layer; a second metal layer arranged on the at least one insulating film and connected with the first metal layer through a contact hole that passes through the at least one insulating film formed in the non-display area; a cover layer arranged on the contact hole and formed to overlap the contact hole; and an encapsulation film formed to cover the display area and the cover layer.

Abstract: Provided is a display apparatus. The display apparatus includes an active area and a bezel area, the display apparatus comprising semiconductor patterns disposed in a third area of the bezel area, an insulating layer disposed on the semiconductor patterns and includes contact holes and dummy holes, a power supply electrode disposed in the third area of the bezel area, overlaps the semiconductor patterns with the insulating layer therebetween, and is connected to the semiconductor patterns through the contact holes, dummy gate lines disposed between the semiconductor patterns and the power supply electrode, overlap the semiconductor pattern to form a first compensation capacitance and overlap the power supply electrode to form a second compensation capacitance, and a dummy semiconductor patterns disposed in the third area of the bezel area, and are connected to the power supply electrode through the dummy holes.

Abstract: A display device may include an active area including a first area having a special-form portion and a second area not having a special-form portion and a bezel area including a third area close to the first area and having a special-form portion and a fourth area close to the second area and not having a special-form portion. Furthermore, the display device may include a first power supply electrode positioned in the third area of the bezel area, a semiconductor pattern positioned in the third area of the bezel area and overlapping the first power supply electrode, and a plurality of dummy gate lines positioned between the semiconductor pattern and the first power supply electrode and overlapping the semiconductor pattern to form a first compensation capacitance and overlapping the first power supply electrode to form a second compensation capacitance.

Abstract: Disclosed is a display device for decreasing a load of a clock line. The display device comprises: a display panel including a plurality of data lines and a plurality of gate lines, and a plurality of pixels in a display area, a gate driver disposed in a non-display area of the display panel and supplying gate signals to the plurality of gate lines, and a gate control line for supplying a gate control signal to the gate driver. The gate control line includes a first gate control line and a second gate control line overlapping the first gate control line with an insulation layer therebetween, the second gate control line being connected to the first gate control line through a first contact hole passing through the insulation layer.

Abstract: A gate driver can include a plurality of stages, each of the plurality of stages including a transistor T1 configured to apply a start signal of a gate-on voltage to a node Q in response to a clock signal and activate the node Q; a transistor T7 configured to supply an emission signal of the gate-on voltage to an output node when a node QA is bootstrapped in synchronization with a timing at which the node Q is activated; a QB controller configured to activate a node QB based on the clock signal, the start signal and a voltage of the node Q; and a transistor T8 configured to supply the emission signal of a gate-off voltage to the output node while the node QB is activated prior to activation of the node Q.

Abstract: Disclosed herein is an organic light-emitting display (OLED) device including: a substrate comprising an active area and an inactive area surrounding the active area; a first planarization layer; a second planarization layer; an organic light-emitting element; an encapsulation layer comprising a first inorganic layer, a second inorganic layer and a first organic member; a first structure in the inactive area and comprising a first support layer made of the same material as the first planarization layer or the second planarization layer, a second structure in the inactive area and comprising a second support layer made of the same material as the first planarization layer or the second planarization layer.

Abstract: Disclosed is a display device which is capable of preventing an encapsulation film from being formed in a scribing line, and a method for manufacturing the same. The display device includes a substrate having a display area provided with pixels, a non-display area surrounding the display area, an encapsulation film including an inorganic film which covers the display area, and a buffer layer. The buffer layer is provided at a predetermined interval from the display area in the non-display area and is brought into contact with the edge of the inorganic film.

Abstract: An electroluminescence display apparatus includes a substrate including a display area and a non-display area. The non-display area includes a bending area and a link area. A first power supply electrode is in the link area. A second power supply electrode is in the non-display area. The second power supply electrode surrounds at least three sides of the display area, and both ends of the second power supply electrode in the link area. A protective layer covers the first power supply electrode and the second power supply electrode in the link area. A first planarizing layer covers one side of the first power supply electrode; and a second planarizing layer is on a contact hole of the protective layer that exposes the first power supply electrode and the second power supply electrode. The first planarizing layer is not on the contact hole.

Abstract: An electroluminescence display apparatus includes a substrate including a display area and a non-display area. The non-display area includes a bending area and a link area. A first power supply electrode is in the link area. A second power supply electrode is in the non-display area. The second power supply electrode surrounds at least three sides of the display area, and both ends of the second power supply electrode in the link area. A protective layer covers the first power supply electrode and the second power supply electrode in the link area. A first planarizing layer covers one side of the first power supply electrode; and a second planarizing layer is on a contact hole of the protective layer that exposes the first power supply electrode and the second power supply electrode. The first planarizing layer is not on the contact hole.

Abstract: Provided is a display apparatus. The display apparatus includes an active area and a bezel area, the display apparatus comprising semiconductor patterns disposed in a third area of the bezel area, an insulating layer disposed on the semiconductor patterns and includes contact holes and dummy holes, a power supply electrode disposed in the third area of the bezel area, overlaps the semiconductor patterns with the insulating layer therebetween, and is connected to the semiconductor patterns through the contact holes, dummy gate lines disposed between the semiconductor patterns and the power supply electrode, overlap the semiconductor pattern to form a first compensation capacitance and overlap the power supply electrode to form a second compensation capacitance, and a dummy semiconductor patterns disposed in the third area of the bezel area, and are connected to the power supply electrode through the dummy holes.

Abstract: A display device is disclosed, which may increase the number of lines arranged in a bending area and at the same time may minimize a crack generated in the bending area. The display device comprises a display area in which pixels are arranged, and a non-display area surrounding the display area, provided with a bending area within the non-display area; a plurality of first lines arranged in the bending area and electrically connected with the pixels; a first organic film arranged on the first lines; a plurality of second lines arranged on the first organic film in the bending area and electrically connected with the pixels; and a second organic film arranged on the second lines, wherein at least one of the first organic film and the second organic film is provided with an open area.

Abstract: An organic light emitting diode display is disclosed in which a flow control pattern of an organic protective layer is disposed to implement a thin bezel. In an active area and a bezel area defined on a substrate, the flow control pattern disposed reduces the flow of a protective layer so as to minimize area size of the bezel area.

Abstract: A display device according to an embodiment of the present disclosure comprises a display panel including a display area having a plurality of pixels connected to a plurality of gate lines, a gate driving circuit in a non-display area adjacent to the display area and including a plurality of stages supplying a gate signal to the plurality of gate lines, and an auxiliary load connected to at least one stage of the plurality of stages in the non-display area in which a number of the plurality of pixels which are connected to at least two gate lines among the plurality of gate lines varies. Therefore, the load applied to the output node of the gate driving circuit is uniformly adjusted so that a screen abnormality of the display device may be suppressed.

Abstract: A gate driver can include a plurality of stages, each of the plurality of stages including a transistor T1 configured to apply a start signal of a gate-on voltage to a node Q in response to a clock signal and activate the node Q; a transistor T7 configured to supply an emission signal of the gate-on voltage to an output node when a node QA is bootstrapped in synchronization with a timing at which the node Q is activated; a QB controller configured to activate a node QB based on the clock signal, the start signal and a voltage of the node Q; and a transistor T8 configured to supply the emission signal of a gate-off voltage to the output node while the node QB is activated prior to activation of the node Q.

Abstract: A display device may include an active area including a first area having a special-form portion and a second area not having a special-form portion and a bezel area including a third area close to the first area and having a special-form portion and a fourth area close to the second area and not having a special-form portion. Furthermore, the display device may include a first power supply electrode positioned in the third area of the bezel area, a semiconductor pattern positioned in the third area of the bezel area and overlapping the first power supply electrode, and a plurality of dummy gate lines positioned between the semiconductor pattern and the first power supply electrode and overlapping the semiconductor pattern to form a first compensation capacitance and overlapping the first power supply electrode to form a second compensation capacitance.

Abstract: A display device is disclosed, which may increase the number of lines arranged in a bending area and at the same time may minimize a crack generated in the bending area. The display device comprises a substrate including a display area on which pixels area arranged, and a non-display area surrounding the display area, provided with a bending within the non-display area; a plurality of first lines arranged in the bending area of the substrate and electrically connected with the pixels; a first organic film arranged on the first lines; a plurality of second lines arranged on the first organic film in the bending area of the substrate and electrically connected with the pixels; and a second organic film arranged on the second lines, wherein at least one of the first organic film and the second organic film is provided with an open area.

Abstract: A display device is disclosed, which may prevent an inorganic film formed in an organic film open area from being damaged and prevent a cathode electrode from being shorted. The display device includes a substrate including a display area on which pixels area arranged, and a non-display area surrounding the display area; a first metal layer formed in the non-display area of the substrate; at least one insulating film arranged on the first metal layer; a second metal layer arranged on the at least one insulating film and connected with the first metal layer through a contact hole that passes through the at least one insulating film formed in the non-display area; a cover layer arranged on the contact hole and formed to overlap the contact hole; and an encapsulation film formed to cover the display area and the cover layer.

Abstract: A display device according to an embodiment of the present disclosure comprises a display panel including a display area having a plurality of pixels connected to a plurality of gate lines, a gate driving circuit in a non-display area adjacent to the display area and including a plurality of stages supplying a gate signal to the plurality of gate lines, and an auxiliary load connected to at least one stage of the plurality of stages in the non-display area in which a number of the plurality of pixels which are connected to at least two gate lines among the plurality of gate lines varies. Therefore, the load applied to the output node of the gate driving circuit is uniformly adjusted so that a screen abnormality of the display device may be suppressed.

Abstract: Disclosed is a display device for decreasing a load of a clock line. The display device comprises: a display panel including a plurality of data lines and a plurality of gate lines, and a plurality of pixels in a display area, a gate driver disposed in a non-display area of the display panel and supplying gate signals to the plurality of gate lines, and a gate control line for supplying a gate control signal to the gate driver. The gate control line includes a first gate control line and a second gate control line overlapping the first gate control line with an insulation layer therebetween, the second gate control line being connected to the first gate control line through a first contact hole passing through the insulation layer.