Abstract: In a semiconductor memory device, and in particular in a NAND-type ROM memory cell, the transistors of a memory cell region and a peripheral circuit portion are manufactured to include a first and second impurity regions. The second impurity region has a higher impurity density impurity than the first impurity region. A third impurity region is added which has a higher impurity density and shallower depth than the impurity density of the first impurity region. Accordingly, the conventional transistor structure of the peripheral circuit portion is maintained while the transistors of the memory cell are optimized to have ideal electrical characteristics, including an increased current driving capability.