Abstract: A semiconductor memory device capable of reducing a data test time in a pipeline is provided. The semiconductor memory device has a pad, data lines, and a data port (DQ) block including a plurality of memory cells. The semiconductor memory device includes a pipeline adapted to output data from selected memory cells of the plurality of memory cells in the DQ block to the pad via the data lines. The pipeline includes a plurality of unit pipeline cells (UPLs) connected in a series. Each of the UPLs is further connected to each of the data lines and is adapted to latch the data, wherein the data is transmitted to a subsequent UPL in the series, if any, so as to sequentially transmit the data to the pad. A comparison controller is connected to a last UPL in the series.

Abstract: A boost voltage generating circuit for a memory device prevents excessive voltage on a word line for a memory cell array and reduces power consumption by utilizing an internal array reference voltage signal as a reference signal for the boost voltage generating circuit. The circuit maintains the boost voltage power supply signal at a predetermined level independently of the voltage level of an internal peripheral reference voltage signal which is applied to a peripheral circuit and which can be increased to increase the speed of the memory device without causing excessive voltage on the word line. The boost voltage generating circuit includes a level detector circuit which receives the array reference voltage signal as a reference signal. The boost voltage generating circuit also includes a pulse generator and a pumping circuit which utilize the array reference voltage signal as a power supply.

Abstract: Integrated circuit memory devices having metal straps include an array of memory devices arranged as a plurality of sub memory blocks (SMB) in a semiconductor substrate, and a plurality of sub word line drivers (SWD) disposed between adjacent sub memory blocks in the substrate. In particular, a plurality of first signal lines at a first metal level (M1) and extending in a first direction on the array are provided. The first signal lines are directly connected to a first sub word line driver at a face of the substrate. In addition, a plurality of second signal lines are provided at a first metal level (M1) and extend in a second direction, orthogonal to the first direction, from the first sub word line driver across at least one sub memory block SMB. At least one metal strap is also provided at a second metal level (M2), above the first metal level.

Abstract: A boosting voltage level detector for a semiconductor memory device which utilizes a boosting voltage the level of which is higher than that of a power supply voltage, which includes a pull-up portion and a pull-down portion. In a preferred embodiment, the pull-up portion includes a PMOS transistor and a first NMOS transistor connected in series between the power supply voltage and an output node, and the pull-down portion includes second and third NMOS transistors connected in series between the output node and ground. The PMOS transistor has a gate electrode which is coupled to ground, and thus functions as a current source. The second NMOS transistor has a gate electrode which is coupled to a reference voltage, and thus functions as a resistor. The gate electrodes of the first and third NMOS transistors are commonly coupled to the boosting voltage. The detector further includes an inverter circuit coupled to the output node.

Abstract: An address buffer circuit for a semiconductor memory device includes first and second address inputs which are selectably connectable to a first node according to first and second address input control signals, respectively. The device also includes first and second switches which are controlled by a refresh mode signal and selectively output a first or second address enable signal. Further, a latch is provided which latches the address signal input to the first node, and outputs the latched address signal in periods of the selected first or second address enable signals.