Patents by Inventor Hyung-Dong Kim

Hyung-Dong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6426902
    Abstract: A redundancy circuit is used to repair a normal column containing a defective normal memory cell. The redundancy circuit comprises a redundancy column containing redundancy memory cells and a plurality of programmable decoders. When any one of the plurality of programmable decoders enters a repair mode, a column pre-decoder for selecting a column containing a normal memory cell is disabled. Each of the programmable decoders can be configured to replace a column containing a defective normal memory cell in a single memory bank or a single memory bank group with a redundancy column. Since a defective column is replaced with a redundancy column in individual banks or bank groups, redundancy efficiency is greatly improved by allowing multiple normal columns containing defective cells to be replaced using a single redundancy column.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: July 30, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hi-choon Lee, Seung-hoon Lee, Hyung-dong Kim
  • Publication number: 20020064078
    Abstract: The present invention discloses a semiconductor memory device and a voltage level control method thereof. The semiconductor memory device comprises multiple sub high voltage generators, multiple control circuits, a high voltage level detecting circuit, and a mode setting circuit. The multiple sub high voltage generators boost the high voltage level. The multiple control circuits control operations of each of the corresponding multiple sub high voltage generators responsive to each of corresponding high voltage detecting signals and to each of corresponding multiple control signals in the test mode. The high voltage level detecting circuit enabled by an active signal, detects the level drop of a high voltage and generates the high voltage detecting signal. The mode setting circuit sets the state of the multiple control signals responsive to the signals from the out side in the test mode.
    Type: Application
    Filed: November 30, 2001
    Publication date: May 30, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyung-Dong Kim, Kwang-Hyun Kim
  • Patent number: 6301171
    Abstract: A semiconductor memory device capable of reducing a data test time in a pipeline is provided. The semiconductor memory device has a pad, data lines, and a data port (DQ) block including a plurality of memory cells. The semiconductor memory device includes a pipeline adapted to output data from selected memory cells of the plurality of memory cells in the DQ block to the pad via the data lines. The pipeline includes a plurality of unit pipeline cells (UPLs) connected in a series. Each of the UPLs is further connected to each of the data lines and is adapted to latch the data, wherein the data is transmitted to a subsequent UPL in the series, if any, so as to sequentially transmit the data to the pad. A comparison controller is connected to a last UPL in the series.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: October 9, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-hyun Kim, Hyung-dong Kim
  • Publication number: 20010010652
    Abstract: A semiconductor memory device capable of reducing a data test time in a pipeline is provided. The semiconductor memory device has a pad, data lines, and a data port (DQ) block including a plurality of memory cells. The semiconductor memory device includes a pipeline adapted to output data from selected memory cells of the plurality of memory cells in the DQ block to the pad via the data lines. The pipeline includes a plurality of unit pipeline cells (UPLs) connected in a series. Each of the UPLs is further connected to each of the data lines and is adapted to latch the data, wherein the data is transmitted to a subsequent UPL in the series, if any, so as to sequentially transmit the data to the pad. A comparison controller is connected to a last UPL in the series.
    Type: Application
    Filed: January 23, 2001
    Publication date: August 2, 2001
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Tae-hyun Kim, Hyung-dong Kim
  • Patent number: 5886933
    Abstract: A boost voltage generating circuit for a memory device prevents excessive voltage on a word line for a memory cell array and reduces power consumption by utilizing an internal array reference voltage signal as a reference signal for the boost voltage generating circuit. The circuit maintains the boost voltage power supply signal at a predetermined level independently of the voltage level of an internal peripheral reference voltage signal which is applied to a peripheral circuit and which can be increased to increase the speed of the memory device without causing excessive voltage on the word line. The boost voltage generating circuit includes a level detector circuit which receives the array reference voltage signal as a reference signal. The boost voltage generating circuit also includes a pulse generator and a pumping circuit which utilize the array reference voltage signal as a power supply.
    Type: Grant
    Filed: June 19, 1997
    Date of Patent: March 23, 1999
    Assignee: Samsung Electronics, Co. Ltd.
    Inventors: Dong-il Seo, Hyung-dong Kim
  • Patent number: 5768174
    Abstract: Integrated circuit memory devices having metal straps include an array of memory devices arranged as a plurality of sub memory blocks (SMB) in a semiconductor substrate, and a plurality of sub word line drivers (SWD) disposed between adjacent sub memory blocks in the substrate. In particular, a plurality of first signal lines at a first metal level (M1) and extending in a first direction on the array are provided. The first signal lines are directly connected to a first sub word line driver at a face of the substrate. In addition, a plurality of second signal lines are provided at a first metal level (M1) and extend in a second direction, orthogonal to the first direction, from the first sub word line driver across at least one sub memory block SMB. At least one metal strap is also provided at a second metal level (M2), above the first metal level.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: June 16, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Il Seo, Hyung-Dong Kim
  • Patent number: 5742197
    Abstract: A boosting voltage level detector for a semiconductor memory device which utilizes a boosting voltage the level of which is higher than that of a power supply voltage, which includes a pull-up portion and a pull-down portion. In a preferred embodiment, the pull-up portion includes a PMOS transistor and a first NMOS transistor connected in series between the power supply voltage and an output node, and the pull-down portion includes second and third NMOS transistors connected in series between the output node and ground. The PMOS transistor has a gate electrode which is coupled to ground, and thus functions as a current source. The second NMOS transistor has a gate electrode which is coupled to a reference voltage, and thus functions as a resistor. The gate electrodes of the first and third NMOS transistors are commonly coupled to the boosting voltage. The detector further includes an inverter circuit coupled to the output node.
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: April 21, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-Dong Kim, Chan-Jong Park
  • Patent number: 5640360
    Abstract: An address buffer circuit for a semiconductor memory device includes first and second address inputs which are selectably connectable to a first node according to first and second address input control signals, respectively. The device also includes first and second switches which are controlled by a refresh mode signal and selectively output a first or second address enable signal. Further, a latch is provided which latches the address signal input to the first node, and outputs the latched address signal in periods of the selected first or second address enable signals.
    Type: Grant
    Filed: January 25, 1996
    Date of Patent: June 17, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-Hong Kim, Jin-Man Han, Hyung-Dong Kim