Abstract: An integrated circuit package may include a board that may support an integrated circuit chip. A post pin may be provided on a surface of the board. The post pin may be electrically connected to the integrated circuit chip. A land pin may be provided on the other surface of the board. The land pin may be electrically connected to the integrated circuit chip.

Abstract: Provided is a semiconductor memory module allowing a filling member formed between a module substrate and memory chips mounted on the module substrate to completely fill the space between the module substrate and the memory chips. According to embodiments of the present invention, the semiconductor memory module includes a module substrate having at least one memory chip mounted on the substrate such that its edges are oblique to major and minor axes bisecting the module substrate. The oblique orientation allows for an improved opening between memory chips formed on the substrate so that the filling member may be properly formed between the module substrate and the memory chips to prevent voids where the filling member is not formed.

Abstract: A stack package may have a plurality of unit packages. Each unit package may include a first substrate, a semiconductor chip, and a second substrate. Conductive supports may stack the second substrate on the first substrate. Conductive bumps may be provided on the bottom surface of the first substrate. An encapsulant may seal the semiconductor chip exposing the top surface of the second substrate. The conductive bumps of an upper unit package may be connected to the second substrate of the lower unit package.

Abstract: A stack package may include a plurality of individual packages arranged in a stack. Each individual package may have a circuit substrate disposed on the upper and lower surfaces of a semiconductor chip. Through bonding wires, a lower circuit substrate may be electrically connected to the semiconductor chip, and an upper circuit substrate may be electrically connected to the lower circuit substrate. An upper package in the stack may be mechanically and electrically connected to the upper circuit substrate of a lower package in the stack through conductive bumps. The semiconductor chip may be surrounded by the upper and the lower circuit substrates, and molding resins. The individual packages may have the same conductive bump layout.

Abstract: An integrated circuit package may include a board that may support an integrated circuit chip. A post pin may be provided on a surface of the board. The post pin may be electrically connected to the integrated circuit chip. A land pin may be provided on the other surface of the board. The land pin may be electrically connected to the integrated circuit chip.

Abstract: Provided is a semiconductor package and method of manufacturing the same. The semiconductor package may include a semiconductor chip, an encapsulant encapsulating the semiconductor chip, a lead unit, and a partially encapsulated by the encapsulating thermal stress buffer which absorbs thermal stress of the semiconductor chip or the encapsulant.

Abstract: Provided is a semiconductor module with enhanced joint reliability. The semiconductor module includes a package, a printed circuit board (PCB), and conductive joint structures for electrically connecting the package with the PCB. The PCB includes at least one buffer layer that can alleviate the thermal deformation of the semiconductor module due to a difference in the coefficient of thermal expansion between the PCB and the conductive joint structures.

Abstract: Example embodiments relate to a semiconductor package having a semiconductor chip provided in a substrate and a method of fabricating the same. The semiconductor package may include a semiconductor substrate having a first through hole and a plurality of second through holes spaced apart from the first through hole. A semiconductor chip having a plurality of pads may be disposed in the first through hole. Solder balls electrically connected to the pads may be attached to end portions of the second through holes. A plurality of the above semiconductor substrates may be stacked to form a multi-chip package.

Abstract: Provided is a semiconductor memory module allowing a filling member formed between a module substrate and memory chips mounted on the module substrate to completely fill the space between the module substrate and the memory chips. According to embodiments of the present invention, the semiconductor memory module includes a module substrate having at least one memory chip mounted on the substrate such that its edges are oblique to major and minor axes bisecting the module substrate. The oblique orientation allows for an improved opening between memory chips formed on the substrate so that the filling member may be properly formed between the module substrate and the memory chips to prevent voids where the filling member is not formed.

Abstract: A stack package may include a plurality of individual packages arranged in a stack. Each individual package may have a circuit substrate disposed on the upper and lower surfaces of a semiconductor chip. Through bonding wires, a lower circuit substrate may be electrically connected to the semiconductor chip, and an upper circuit substrate may be electrically connected to the lower circuit substrate. An upper package in the stack may be mechanically and electrically connected to the upper circuit substrate of a lower package in the stack through conductive bumps. The semiconductor chip may be surrounded by the upper and the lower circuit substrates, and molding resins. The individual packages may have the same conductive bump layout.

Abstract: Example embodiments relate to a semiconductor package, a method of manufacturing the semiconductor package, a stacked semiconductor package including the semiconductor package, and a method of manufacturing the stacked semiconductor package. Other example embodiments relate to a semiconductor package having a structure that allows at least two packages to be stacked, a method of manufacturing the semiconductor package, a stacked semiconductor package including the semiconductor package, and a method of manufacturing the stacked semiconductor package.

Abstract: A stack package may have a plurality of unit packages. Each unit package may include a first substrate, a semiconductor chip, and a second substrate. Conductive supports may stack the second substrate on the first substrate. Conductive bumps may be provided on the bottom surface of the first substrate. An encapsulant may seal the semiconductor chip exposing the top surface of the second substrate. The conductive bumps of an upper unit package may be connected to the second substrate of the lower unit package.

Abstract: An integrated circuit package may include a board that may support an integrated circuit chip. A post pin may be provided on a surface of the board. The post pin may be electrically connected to the integrated circuit chip. A land pin may be provided on the other surface of the board. The land pin may be electrically connected to the integrated circuit chip.