Patents by Inventor Hyung-Ho Cho
Hyung-Ho Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128915Abstract: Disclosed is a motor driving apparatus including: a motor; an inverter including a switching element for driving the motor; a controller for controlling the switching element; a resolver including an excitation winding and a detection winding; and a resolver chip applying an excitation signal to the excitation winding by inputting a periodic signal from the controller, and receiving a feedback signal from the detection winding, wherein the resolver chip determines the number of rotations of the motor based on a change in a pulse width of a detection signal resulting from a comparison between a voltage of the feedback signal and a preset voltage, and output a signal to the inverter for setting an inertial driving control mode according to the number of rotations of the motor in a failure state of the controller.Type: ApplicationFiled: October 17, 2023Publication date: April 18, 2024Applicant: HYUNDAI MOBIS CO., LTD.Inventors: Tae Hwan KANG, Hyung Min PARK, Joo Won PARK, Beom Cheol CHO, Yun Ho CHOI, Yeon Ho KIM, Won Hee JO
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Patent number: 11929389Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.Type: GrantFiled: May 19, 2021Date of Patent: March 12, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-soo Kim, Seung-min Ryu, Chang-su Woo, Hyung-suk Jung, Kyu-ho Cho, Youn-joung Cho
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Publication number: 20240069524Abstract: Disclosed is an apparatus for excitation signal generation for a resolver. The apparatus includes a sine wave generator that generates a sine wave based on a square wave, an amplifier that amplifies the sine wave, a differential signal generator that converts, into a differential signal, the amplified sine wave, a driver that inputs the differential signal to a coil, and a processor that generates an excitation signal by increasing a voltage of the sine wave from a start voltage to a target voltage through at least one of the sine wave generator and the amplifier based on a transient current that flows into the coil in a transient response interval.Type: ApplicationFiled: December 27, 2022Publication date: February 29, 2024Applicant: HYUNDAI MOBIS CO., LTD.Inventors: Yun Ho CHOI, Hyung Min PARK, Joo Won PARK, Yeon Ho KIM, Won Hee JO, Tae Hwan KANG, Beom Cheol CHO
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Patent number: 11715708Abstract: A semiconductor package includes a substrate and a semiconductor chip disposed over the substrate. The substrate includes: a base layer including an upper surface facing the semiconductor chip; an upper ground electrode plate disposed over the upper surface of the base layer and configured to transmit a ground voltage to the semiconductor chip; and a dummy power pattern disposed in the upper ground electrode plate and having a side surface which is surrounded by the upper ground electrode plate and is spaced apart from the upper ground electrode plate with an insulating material between the dummy power pattern and the upper ground electrode plate. A ground voltage transmission path from the upper ground electrode plate to the semiconductor chip is spaced apart from the dummy power pattern.Type: GrantFiled: October 11, 2021Date of Patent: August 1, 2023Assignee: SK hynix Inc.Inventors: Jae Hoon Lee, Hyung Ho Cho
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Patent number: 11682643Abstract: A semiconductor chip includes a chip body including a signal input/output circuit unit, a chip pad unit disposed on one surface of the chip body and including first and second chip pads having different surface areas from each other, and a chip pad selection circuit unit disposed in the chip body and electrically connected to the signal input/output circuit unit and the chip pad unit. The chip pad selection circuit unit is configured to select one chip pad of the first and second chip pads and electrically connect the selected one chip pad to the signal input/output circuit unit.Type: GrantFiled: April 26, 2021Date of Patent: June 20, 2023Assignee: SK hynix Inc.Inventors: Ju Il Eom, Woo Jin Lee, Hyung Ho Cho
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Publication number: 20220173735Abstract: A semiconductor chip includes a chip body including a signal input/output circuit, a chip pad structure disposed on a surface of the chip body, the chip pad structure including first and second chip pads, the two chip pads having different surface areas, and a chip pad selection circuit disposed in the chip body and electrically connected to the signal input/output circuit and the chip pad structure. The chip pad selection circuit is configured to selectively and electrically connect one of the first and second chip pads to the signal input/output circuit.Type: ApplicationFiled: October 11, 2021Publication date: June 2, 2022Applicant: SK hynix Inc.Inventors: Ju Il EOM, Woo Jin LEE, Hyung Ho CHO
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Publication number: 20220173061Abstract: A semiconductor chip includes a chip body including a signal input/output circuit unit, a chip pad unit disposed on one surface of the chip body and including first and second chip pads having different surface areas from each other, and a chip pad selection circuit unit disposed in the chip body and electrically connected to the signal input/output circuit unit and the chip pad unit. The chip pad selection circuit unit is configured to select one chip pad of the first and second chip pads and electrically connect the selected one chip pad to the signal input/output circuit unit.Type: ApplicationFiled: April 26, 2021Publication date: June 2, 2022Applicant: SK hynix Inc.Inventors: Ju Il EOM, Woo Jin LEE, Hyung Ho CHO
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Publication number: 20220028806Abstract: A semiconductor package includes a substrate and a semiconductor chip disposed over the substrate. The substrate includes: a base layer including an upper surface facing the semiconductor chip; an upper ground electrode plate disposed over the upper surface of the base layer and configured to transmit a ground voltage to the semiconductor chip; and a dummy power pattern disposed in the upper ground electrode plate and having a side surface which is surrounded by the upper ground electrode plate and is spaced apart from the upper ground electrode plate with an insulating material between the dummy power pattern and the upper ground electrode plate. A ground voltage transmission path from the upper ground electrode plate to the semiconductor chip is spaced apart from the dummy power pattern.Type: ApplicationFiled: October 11, 2021Publication date: January 27, 2022Applicant: SK hynix Inc.Inventors: Jae Hoon LEE, Hyung Ho CHO
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Patent number: 11183470Abstract: A semiconductor package includes a substrate and a semiconductor chip disposed over the substrate. The substrate includes: a base layer including an upper surface facing the semiconductor chip; an upper ground electrode plate disposed over the upper surface of the base layer and configured to transmit a ground voltage to the semiconductor chip; and a dummy power pattern disposed in the upper ground electrode plate and having a side surface which is surrounded by the upper ground electrode plate and is spaced apart from the upper ground electrode plate with an insulating material between the dummy power pattern and the upper ground electrode plate. A ground voltage transmission path from the upper ground electrode plate to the semiconductor chip is spaced apart from the dummy power pattern.Type: GrantFiled: July 9, 2020Date of Patent: November 23, 2021Assignee: SK hynix Inc.Inventors: Jae Hoon Lee, Hyung Ho Cho
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Publication number: 20210327830Abstract: A semiconductor package includes a substrate and a semiconductor chip disposed over the substrate. The substrate includes: a base layer including an upper surface facing the semiconductor chip; an upper ground electrode plate disposed over the upper surface of the base layer and configured to transmit a ground voltage to the semiconductor chip; and a dummy power pattern disposed in the upper ground electrode plate and having a side surface which is surrounded by the upper ground electrode plate and is spaced apart from the upper ground electrode plate with an insulating material between the dummy power pattern and the upper ground electrode plate. A ground voltage transmission path from the upper ground electrode plate to the semiconductor chip is spaced apart from the dummy power pattern.Type: ApplicationFiled: July 9, 2020Publication date: October 21, 2021Applicant: SK hynix Inc.Inventors: Jae Hoon LEE, Hyung Ho CHO
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Patent number: 9953965Abstract: A semiconductor package may include a DRAM chip mounted on a substrate; an interposer stacked over the DRAM chip and including redistribution structures; a nonvolatile memory chip stacked over the interposer; a memory controller chip mounted on the substrate, and including a control circuit for controlling the nonvolatile memory chip and first pads and second pads electrically coupled to the control circuit; first conductive coupling members configured to electrically couple bonding pads of the nonvolatile memory chip to the redistribution structures; second conductive coupling members configured to electrically couple the redistribution structures to the first pads; and third conductive coupling members configured to electrically couple the second pads to the substrate.Type: GrantFiled: July 11, 2016Date of Patent: April 24, 2018Assignee: SK hynix Inc.Inventors: Gi Guk Park, Hyung Ho Cho, Tae Lim Song
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Publication number: 20170278833Abstract: A semiconductor package may include a DRAM chip mounted on a substrate; an interposer stacked over the DRAM chip and including redistribution structures; a nonvolatile memory chip stacked over the interposer; a memory controller chip mounted on the substrate, and including a control circuit for controlling the nonvolatile memory chip and first pads and second pads electrically coupled to the control circuit; first conductive coupling members configured to electrically couple bonding pads of the nonvolatile memory chip to the redistribution structures; second conductive coupling members configured to electrically couple the redistribution structures to the first pads; and third conductive coupling members configured to electrically couple the second pads to the substrate.Type: ApplicationFiled: July 11, 2016Publication date: September 28, 2017Inventors: Gi Guk PARK, Hyung Ho CHO, Tae Lim SONG
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Publication number: 20070195255Abstract: An assembled substrate for a liquid crystal panel that may prevent failures to pads, or the like, when transferring the assembled substrate with cutting channels to a predetermined work station, a method of cutting the assembled substrate, and a liquid crystal panel manufactured by the method. The assembled substrate includes a thin film transistor (TFT) mother substrate including a plurality of TFT array substrates corresponding to liquid crystal unit panels, a color filter mother substrate coupled with the TFT mother substrate and including a plurality of color filter substrates corresponding to the liquid crystal unit panels, and dummy seal patterns interposed between the TFT mother substrate and the color filter mother substrate. The dummy seal patterns overlap with cutting channels for cutting the TFT mother substrate or the color filter mother substrate into the liquid crystal unit panels.Type: ApplicationFiled: December 4, 2006Publication date: August 23, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-Ho Cho, Jang-II Kim