Patents by Inventor Hyung-Iae Eun

Hyung-Iae Eun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-chip package having a stacked plurality of different sized semiconductor chips, and method of manufacturing the same
    Patent number: 9397034
    Abstract: Provided is a multi-chip package in which a plurality of semiconductor chips having different sizes are stacked. A multi-chip package may include a substrate, and a plurality of semiconductor chips stacked on the substrate, each of the plurality of semiconductor chips having a different size. Each of the plurality of semiconductor chips including a pad group and a reference region associated with the pad group, each pad group having a plurality of pads, and the plurality of pads in each pad group located at same coordinates with respect to the associated reference region, and each of the plurality of semiconductor chips having their reference regions vertically aligned.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: July 19, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyung-Iae Eun
  • Multi-chip package having a stacked plurality of different sized semiconductor chips, and method of manufacturing the same
    Patent number: 8395259
    Abstract: Provided is a multi-chip package in which a plurality of semiconductor chips having different sizes are stacked. A multi-chip package may include a substrate, and a plurality of semiconductor chips stacked on the substrate, each of the plurality of semiconductor chips having a different size. Each of the plurality of semiconductor chips including a pad group and a reference region associated with the pad group, each pad group having a plurality of pads, and the plurality of pads in each pad group located at same coordinates with respect to the associated reference region, and each of the plurality of semiconductor chips having their reference regions vertically aligned.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: March 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyung-Iae Eun